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1.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xxxvii, 452 p. ; 28 cm
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Foreword
VTS 20th Anniversary Page
Acknowledgements
Organizing Committee
Steering Committee
Program Committee
Reviewers
Test Technology Technical Council
Test Technology Educational Program: Overview of Tutorials
Plenary Session
Welcome Message
Keynote Address
Program Introduction
Plenary Address: Business and Technical Challenges for Testing the Ghz Age
Microprocessor Test / Session 1:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC Instruction Set Architecture / N. Tendolkar ; R. Raina ; R. Woltenberg ; X. Lin ; B. Swanson ; G. Aldrich
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs / A. Pandey ; J. Patel
Scan Islands--A Scan Partitioning Architecture and Its Implementation on the Alpha 21364 Processor / D. Bhavsar ; R. Davies
Applications of Very Low Voltage and Slow Speed Testing / Session 2:
Very Low Voltage Testing of SOI Integrated Circuits / E. MacDonald ; N. Touba
Performance Comparison of VLV, ULV, and ECR Tests / W. Jiang ; E. Peterson
Experimental Results for Slow-Speed Testing / C.-W. Tseng ; J. Li ; E. McCluskey
Innovations in Test Automation / IP Session 1:
Advancements in Scan-Based Testing / Session 3:
Scan-Path with Directly Duplicated and Inverted Duplicated Registers / M. Goessel ; A. Singh ; E. Sogomonyan
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits / A. El-Maleh ; A. Al-Suwaiyan
Logic BIST and Scan Test Techniques for Multiple Identical Blocks / K. Arabi
Burn-in Reduction or Alternatives / Session 4:
Statistical Post-Processing at Wafersort--An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies / R. Madge ; M. Rehani ; K. Cota ; W. Daasch
Yield-Reliability Modeling: Experimental Verification and Application to Burn-in Reduction / T. Barnett ; M. Grady ; K. Purdy
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-Based I[subscript DDQ] Testing for Burn-in Reduction / S. Sabade ; D. Walker
DFT Testers 1 / IP Session 2:
A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?
Test Set Compression Techniques / Session 5:
How Effective Are Compression Codes for Reducing Test Data Volume? / A. Chandra ; K. Chakrabarty ; R. Medina
Test Vector Compression Using EDA-ATE Synergies / A. Khoche ; E. Volkerink ; J. Rivoir ; S. Mitra
On Test Data Volume Reduction for Multiple Scan Chain Designs / S. Reddy ; K. Miyase ; S. Kajihara ; I. Pomeranz
Analog BIST / Session 6:
Spectrum-Based BIST in Complex SoCs / G. Kasturirangan ; M. Hsiao
A Self Calibrated ADC BIST Methodology / H.-K. Chen ; C.-H. Wang ; C.-C. Su
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus / C.-K. Ong ; K.-T. Cheng
DFT Testers 2 / IP Session 3:
A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?
Increased Efficiency Testing / Session 7:
Testing High-Speed SoCs Using Low-Speed ATEs / M. Nourani ; J. Chin
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs / M. Iyer
On Using Efficient Test Sequences for BIST / R. David ; P. Girard ; C. Landrault ; S. Pravossoudovitch ; A. Virazel
Controlling and Reducing Test Power / Session 8:
Controlling Peak Power during Scan Testing / R. Sankaralingam
Test Vector Modification for Power Reduction during Scan Testing / K. Ishida
Test Power Reduction through Minimization of Scan Chain Transitions / O. Sinanoglu ; I. Bayraktaroglu ; A. Orailoglu
Wireless Test / IP Session 4:
Panel / Special Session 1:
Analog & Mixed Signal BIST: Too Much, Too Little, Too Late?
Test as a Key Enabler for Faster Yield Ramp-Up / Special Session 2:
Diagnosis / Session 9:
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits / M. Amyeen ; W. Fuchs
Diagnosis of Sequence-Dependent Chips
Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation / S.-Y. Huang
Analog Circuit Testing / Session 10:
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus / J. Calvano ; V. Alves ; M. Lubazewski ; A. Mesquita
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division / T. Yamaguchi ; M. Soma ; L. Malarsie ; M. Ishida ; H. Musha
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis / S. Ozev
High Level Test Techniques / Session 11:
Instruction-Based Self-Testing of Processor Cores / N. Kranitis ; D. Gizopoulos ; A. Paschalis ; Y. Zorian
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation / L. Berrojo ; F. Corno ; L. Entrena ; I. Gonzalez ; C. Lopez ; M. Sonza Reorda ; G. Squillero
Program Slicing for Hierarchical Test Generation / V. Vedula ; J. Abraham ; J. Bhadra
SoC Test Infrastructure / Session 12:
Design for Testability and Testing of IEEE 1149.1 Tap Controller / S. Makar
On Using Rectangle Packing for SoC Wrapper/TAM Co-optimization / V. Iyengar ; E. Jan Marinissen
Cluster-Based Test Architecture Design for System-on-Chip / S. Goel
Multi-GigaHertz Testing Challenges and Solutions / IP Session 5:
Test Tools and Algorithms / Session 13:
Exploiting Dominance and Equivalence Using Fault Tuples / K. Dwarakanath ; R. Blanton
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? / N. Krishnamurthy ; M. Abadir
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics / K.-L. Cheng ; J.-C. Yeh ; C.-W. Wang ; C.-T. Huang ; C.-W. Wu
Supply Current Testing / Session 14:
Eigen-Signatures for Regularity-Based I[subscript DDQ] Testing / Y. Okuda
Speeding-up I[subscript DDQ] Measurements / C. Thibeault
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform / S. Bhunia ; K. Roy
IEEE P1500 in Practice / IP Session 6:
Debating the Future of Burn-In / Special Session 3:
Hot Topic / Special Session 4:
Beyond CMOS
Embedded Tutorial / Special Session 5:
Challenges of Mixed-Signal Board Design and Test / G. Roberts
Test Pattern Generation / Session 15:
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits / S. Ohtake ; S. Miwa ; H. Fujiwara
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits / T. Hosokawa ; H. Date ; M. Muraoka
Test Pattern Generation for Signal Integrity Faults on Long Interconnects / A. Attarha
Tester Hardware Modeling and Improvements / Session 16:
Improved Test Monitor Circuit in Power Pin DfT / R. Schuttert ; F. de Jong ; B. Kup
Measuring Stray Capacitance on Tester Hardware / A. Halder ; P. Variyam ; A. Chatterjee ; J. Ridley
Power Supply Transient Signal Analysis under Real Process and Test Hardware Models / J. Plusquellic ; A. Gattiker
FPGA Test Practices / IP Session 7:
Fault Modeling & Extraction / Session 17:
Layout Analysis to Extract open Nets Caused by Systematic Failure Mechanisms / S. Chakravarty ; K. Komeyli ; E. Savage ; M. Carruthers ; B. Stastny ; S. Zachariah
Fault Models for Speed Failures Caused by Bridges and Opens / A. Jain
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits / R. Kundu
Memory Testing / Session 18:
Testing and Diagnosing Embedded Content Addressable Memories / J.-F. Li ; R.-S. Tzeng
Testing Static and Dynamic Faults in Random Access Memories / S. Hamdioui ; Z. Al-Ars ; Ad J. van de Goor
Approximating Infinite Dynamic Behavior for DRAM Cell Defects
IP Session 8
Validation & Test of Network Processors and ASICs
Test-Cost Reduction / Session 19:
Test Economics for Multi-site Test with Modern Cost Reduction Techniques / K. Hilliges
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects / K. Sekar ; S. Dey
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions / P. Gonciari ; B. Al-Hashimi ; N. Nicolici
Oscillation - Based Test / Session 20:
Practical Solutions for the Application of the Oscillation-Based-Test: Start-up and On-Chip Evaluation / D. Vazquez ; G. Huertas ; G. Leger ; A. Rueda ; J. Huertas
Evaluation of the Oscillation-Based Test Methodology for Micro-Electro-Mechanical Systems / V. Beroulle ; Y. Bertrand ; L. Latorre ; P. Nouet
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? / Special Session 6:
Challenges in Nanometric Technology Scaling: Trends and Projections / Special Session 7:
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? / Special Session 8:
Author Index
Foreword
VTS 20th Anniversary Page
Acknowledgements
2.

図書

図書
[sponsored by the IEEE Computer Society Test Technology Technical Council, the IEEE Computer Society Technical Committee on Fault-Tolerant Computing]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xiii, 441 p. ; 23 cm
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Message from the Symposium Chairs
Organizing Committee
Program Committee
Yield I / Session 1:
Manufacturability Analysis of Analog CMOS ICs Through Examination of Multiple Layout Solutions / P. Khademsameni ; M. Syrzycki
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI / A. Vassighi ; O. Semenov ; M. Sachdev ; A. Keshavarzi
Yield Estimates for the TESH Multicomputer Network / B. M. Maziarz ; V. K. Jain
Crosstalk Faults / Session 2:
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis / P. Civera ; L. Macchiarulo ; M. Violante
A Test-Vector Generation Methodology for Crosstalk Noise Faults / H. Hashempour ; Y.-B. Kim ; N. Park
Self-Checking and ABFT / Session 3:
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri ; V. Piuri
Designing Self-Checking FPGAs Through Error Detection Codes / C. Bolchini ; F. Salice ; D. Sciuto
Self-Checking 1-out-of-n CMOS Current-Mode Checker / J. Mathew ; E. Dubrova
Partially Duplicated Code-Disjoint Carry-Skip Adder / D. Marienfeld ; V. Ocheretnij ; M. Gossel ; E. S. Sogomonyan
Input Ordering in Concurrent Checkers to Reduce Power Consumption / K. Mohanram ; N. A. Touba
Fault Simulation and Injection I / Session 4:
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs / D. Alexandrescu ; L. Anghel ; M. Nicolaidis
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied / R. Velazco ; A. Corominas ; P. Ferreyra
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm / H.-B. Wang ; S.-Y. Huang ; J.-R. Huang
Scan Design / Session 5:
Scan Architecture for Shift and Capture Cycle Power Reduction / P. M. Rosinger ; B. M. Al-Hashimi ; N. Nicolici
Inserting Test Points to Control Peak Power During Scan Testing / R. Sankaralingam
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits / C.-H. Cheng
Test Application / Session 6:
Matrix-Based Test Vector Decompression Using an Embedded Processor / K. J. Balakrishnan
Data Compression for System-on-Chip Testing Using ATE / F. Karimi ; W. Meleis ; Z. Navabi ; F. Lombardi
Test Generation / Session 7:
Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-At and Transition Faults / J. Dworak ; J. Wingfield ; B. Cobb ; S. Lee ; L.-C. Wang ; M. R. Mercer
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE / F. J. Meyer
Testing Digital Circuits with Constraints / A. A. Al-Yamani ; S. Mitra ; E. J. McCluskey
Concurrent Error Detection / Session 8:
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits / C. Metra ; S. Di Francescantonio ; G. Marrale
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling / F. M. Goncalves ; M. B. Santos ; I. C. Teixeira ; J. P. Teixeira
A Memory Overhead Evaluation of the Interleaved Signature Instruction Stream / F. Rodriguez ; J. C. Campelo ; J. J. Serrano
Fault-Tolerant CAM Architectures: A Design Framework / M. G. Sami ; R. Stefanelli
Fault Simulation and Injection II / Session 9:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes / L. Antoni ; R. Leveugle ; B. Feher
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques / S. Blanc ; J. Gracia ; P. J. Gil
Fault List Compaction Through Static Timing Analysis for Efficient Fault Injection Experiments / M. Sonza Reorda
Interconnect / Session 10:
Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH / S. Horiguchi ; Y. Miura
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations / X. Sun ; A. Alimohammad ; P. Trouborst
Testing Layered Interconnection Networks
Yield II / Session 11:
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure / Y. Hamamura ; K. Nemoto ; T. Kumazawa ; H. Iwata ; K. Okuyama ; S. Kamohara ; A. Sugimoto
Yield Modeling of a WSI Telcom Router Architecture / B. Qiu ; Y. Savaria ; M. Lu ; C. Wang ; C. Thibeault
System-on-Chip Test / Session 12:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation / O. Sinanoglu ; A. Orailoglu
Adaptive Test Scheduling in SoC's by Dynamic Partitioning / D. Zhao ; S. Upadhyaya
Feasibility of CED / Session 13:
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies / T. Verdel ; Y. Makris
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage / S. J. Piestrak
Test / Session 14:
Emulation-Based Design Errors Identification / A. CasteInuovo ; A. Fin ; F. Fummi ; F. Sforza
A New Functional Fault Model for FPGA Application-Oriented Testing / M. Rebaudengo
Neighbor Current Ratio (NCR): A New Metric for I[subscript DDQ] Data Analysis / S. S. Sabade ; D. M. H. Walker
CMOS Standard Cells Characterization for I[subscript DDQ] Testing / W. A. Pleskacz ; T. Borejko ; W. Kuzmicz
On-Chip Jitter Measurement for Phase Locked Loops / T. Xia ; J.-C. Lo
Neural Networks-Based Parametric Testing of Analog IC / V. Stopjakova ; D. Micusik ; L. Benuskova ; M. Margala
Reliable and Repairable Memories / Session 15:
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems / M. Choi ; Y. B. Kim
Repairability Evaluation of Embedded Multiple Region DRAMs / Y. Chang
Author Index
TTTC Information
Message from the Symposium Chairs
Organizing Committee
Program Committee
3.

図書

図書
sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section
出版情報: Washington, D.C. : International Test Conference, c2002  xvi, 1250 p. ; 29 cm
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4.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Fault-Tolerant Computing, IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xiii, 468 p. ; 23 cm
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5.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council, Tenth Anniversary Committee of Asian Test Symposium
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xii, 374 p. ; 28 cm
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Preface
Editorial Board
ATS 1992
An Approach to Design-for-Testability for Memory Embedding Logic LSIs / K. Hatayama ; T. Hayashi ; M. Takakura ; T. Suzuki ; S. Michishita ; H. Satoh
Synthesis for Testability of PLA Based Finite State Machines / M. Avedillo ; J. Quintana ; J. Huertas
A Concurrent Fault Detection Method for Superscalar Processors / A. Pawlovsky ; M. Hanawa
A Method of Diagnosing Logical Faults in Combinational Circuits / K. Yamazaki ; T. Yamada
Reduction of Dynamic Memory Usage in Concurrent Fault Simulation for Synchronous Sequential Circuits / K. Kim ; K. Saluja
ATS 1993
Test Set Partitioning and Dynamic Fault Dictionaries for Sequential Circuits / P. Ryan ; W. Fuchs
A Two-Phase Fault Simulation Scheme for Sequential Circuits / W. Wu ; C. Lee ; J. Chen
GID-Testable Two-Dimensional Sequential Arrays for Self-Testing / W. Huang ; F. Lombardi ; M. Lu
A Global BIST Methodology / T. Gheewala ; H. Sucar ; P. Varma
On Properties and Implementations of Inverting ALSC for Use in Built-in Self-Testing / K. Furuya ; P. Koh ; E. McCluskey
ATS 1994
Efficient Test Sequence Generation for Localization of Multiple Faults in Communication Protocols / Y. Kakuda ; H. Yukitomo ; S. Kusumoto ; T. Kikuno
Design of Random Pattern Testable Floating Point Adders / J. Rajski ; J. Tyszer
Testability Considerations in Technology Mapping / I. Pomeranz ; S. Reddy
Analysis and Improvement of Testability Measure Approximation Algorithms / J. Bitner ; J. Jain ; J. Abraham ; D. Fussell
Efficiency Improvements for Multiple Fault Diagnosis of Combinational Circuits / N. Yanagida ; H. Takahashi ; Y. Takamatsu
Boolean Process--An Analytical Approach to Circuit Representation / Y. Min
ATS 1995
Software Transformations for Sequential Test Generation / A. Balakrishnan ; S. Chakradhar
DC Control and Observation Structures for Analog Circuits / Y.-R. Shieh ; C.-W. Wu
Universal Test Complexity of Field-Programmable Gate Arrays / T. Inoue ; H. Fujiwara ; H. Michinishi ; T. Yokohira ; T. Okamoto
A Design-for-Test Technique for Multi-stage Analog Circuits / M. Renovell ; F. Azais ; Y. Bertrand
Fanout Fault Analysis for Digital Logic Circuits / W. Shen ; B. Chen
Theory and Applications of Cellular Automata for Synthesis of Easily Testable Combinational Logic / S. Nandi ; P. Chaudhuri
Low Power Design and Its Testability / H. Ueda ; K. Kinoshita
ATS 1996
Redundancy Identification Using Transitive Closure / V. Agrawal ; M. Bushnell ; Q. Lin
A Consistent Scan Design System for Large-Scale ASICs / Y. Konno ; K. Nakamura ; T. Bitoh ; K. Saga ; S. Yano
Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults / K.-J. Lee ; J.-J. Tang ; T.-C. Huang ; C.-L. Tsai
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique / Y. Higami ; S. Kajihara
An Efficient Compact Test Generator for I[subscript DDQ] Testing / H. Kondo ; K.-T. Cheng
ATS 1997
FaultMaxx: A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits / N. Ben-Hamida ; K. Saab ; D. Marche ; B. Kaminska
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs / S. Miyazaki
Testing for the Programming Circuit of LUT-Based FPGAs
Test Length for Random Testing of Sequential Machines Application to RAMs / R. David
A Genetic Algorithm for Computation of Initialization Sequences for Synchronous Sequential Circuits / F. Corno ; P. Prinetto ; M. Rebaudengo ; M. Reorda ; G. Squillero
On Chip Weighted Random Patterns / J. Savir
ATS 1998
Vector Restoration Using Accelerated Validation and Refinement / S. Bommu ; K. Doreswamy
March LA: A Test for All Linked Memory Faults / A. van de Goor ; G. Gaydadjiev ; V. Yarmolik ; V. Mikitjuk
Test Cycle Count Reduction in a Parallel Scan BIST Environment / B. Ayari
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level / C.-H. Chiang ; S. Gupta
False-Path Removal Using Delay Fault Simulation / M. Gharaybeh
A Ring Architecture Strategy for BIST Test Pattern Generation / C. Fagot ; O. Gascuel ; P. Girard ; C. Landrault
ATS 1999
High Resolution CD-SEM System / Y. Ose ; M. Ezumi ; H. Todokoro
An Evaluation of Test Generation Algorithms for Combinational Circuits / S. Xu ; T. Frank
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits / H.-C. Liang
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption / L. Guiller ; S. Pravossoudovitch
New DFT Techniques of Non-scan Sequential Circuits with Complete Fault Efficiency / D. Das ; S. Ohtake
ATS 2000
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen ; M. Breuer
A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue ; E. Gizdarski
Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris ; J. Collins ; A. Orailoglu
A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen
Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang
ATS 2001
Short Circuit Faults in State-of-the-Art ADCs--Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes
EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara
Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan
Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-Ul-Amin
Author Index
Preface
Editorial Board
ATS 1992
6.

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図書
sponsored by IEEE Computer Society Test Technology Technical Council ; in cooperation with Technical Group on Fault Tolerant Systems ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxvi, 473 p. ; 28 cm
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Message from the Symposium Chair
Message from the Program Chair
Message from the 10th Anniversary Committee Chair
ATS 2000 Best Paper Award
Asian Test Committee
The 10th Asian Test Symposium Committee
Program Committee
Reviewers
TTTC Activities Board
Plenary Session: Keynote Address
DFT for High-Quality Low Cost Manufacturing Test / Janusz Rajski (Mentor Graphics Corporation, USA)
Design for Testability / Session 1A:
Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-UI-Amin ; S. Ohtake ; H. Fujiwara
A Multiple Phase Partial Scan Design Method / D. Xiang ; Y. Xu
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States / H. Yotsuyanagi ; S. Hata ; M. Hashizume ; T. Tamesada
Fault Modeling for Memories / Session 1B:
Tests for Resistive and Capacitive Defects in Address Decoders / M. Klaus ; Ad J. van de Goor
Detecting Unique Faults in Multi-port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers
A Memory Specific Notation for Fault Modeling / Z. Al-Ars ; J. Braun ; D. Richter
Diagnosis / Session 1C:
On Pass/Fail Dictionaries for Scan Circuits / I. Pomeranz
Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA / M. Gossel ; V. Ocheretnij ; S. Chakrabarty
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits / H. Takahashi ; M. Phadoongsidhi ; Y. Higami ; K. Saluja ; Y. Takamatsu
ATPG / Session 2A:
Test Generation for Double Stuck-at Faults / N. Takahashi
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems / T. Shinogi ; T. Kanbayashi ; T. Yoshikawa ; S. Tsuruoka ; T. Hayashi
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits / R. Guo ; S. Reddy
Embedded Memory Test / Session 2B:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip / K.-L. Cheng ; C.-M. Hsueh ; J.-R. Huang ; J.-C. Yeh ; C.-T. Huang ; C.-W. Wu
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis / D. Appello ; F. Corno ; M. Giovinetto ; M. Rebaudengo ; M. Reorda
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters / C.-W. Wang ; R.-S. Tzeng ; C.-F. Wu ; S.-Y. Huang ; S.-H. Lin ; H.-P. Wang
I[subscript DDQ] Test and Diagnosis / Session 2C:
I[subscript DDQ] Sensing Technique for High Speed I[subscript DDQ] Testing / T. Takeda ; M. Ichimiya ; Y. Miura ; K. Kinoshita
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application
An Approach to Improve the Resolution of Defect-Based Diagnosis / I. Yamazaki ; H. Yamanaka ; T. Ikeda ; M. Takakura ; Y. Sato
Test Compaction / Session 3A:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits
A Method of Static Compaction of Test Stimuli / K. Boateng ; H. Konishi ; T. Nakata
Dynamic Test Compression Using Statistical Coding / H. Ichihara ; A. Ogawa ; T. Inoue ; A. Tamura
Pattern Generation for Memory Test / Session 3B:
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing / M.-J. Wang ; R.-L. Jiang ; J.-W. Hsia ; C.-H. Wang ; J. Chen
Memory Read Faults: Taxonomy and Automatic Test Generation / A. Benso ; S. Di Carlo ; G. Di Natale ; P. Prinetto
Simulation and Development of Short Transparent Tests for RAM / S. Demidenko ; A. van de Goor ; S. Henderson ; P. Knoppers
Virtual Tester and Beam Testing / Session 3C:
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions / J. Hirase
EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara
Benefits of Phase Interference Detection to IC Waveform Probing / J. Block ; W. Lo ; C. Shaw
SoC Test Access Mechanism / Session 4A:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability / T. Yoneda
Compaction Schemes with Minimum Test Application Time / O. Sinanoglu ; A. Orailoglu
Design of an Optimal Test Access Architecture Using a Genetic Algorithm / Z. Ebadi ; A. Ivanov
RTL ATPG / Session 4B:
An RT-Level ATPG Based on Clustering of Circuit States / H. Li ; Y. Min ; Z. Li
An Approach to RTL Fault Extraction and Test Generation / Z. Yin ; X. Li
Effective Techniques for High-Level ATPG / G. Cumani ; G. Squillero
Delay Test / Session 4C:
An Efficient Method to Identify Untestable Path Delay Faults / Y. Shao ; S. Kajihara
SpeedGrade: An RTL Path Delay Fault Simulator / K. Kim ; R. Jayabharathi ; C. Carstens
Test Generation for Multiple-Threshold Gate-Delay Fault Model / M. Nakao ; Y. Kiyoshige ; K. Hatayama ; T. Nagumo
SoC Test Scheduling / Session 5A:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores / Y. Bonhomme ; P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch
Test Scheduling and Scan-Chain Division under Power Constraint / E. Larsson ; Z. Peng
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan
FSM Test / Session 5B:
A Unified Scheme for Designing Testable State Machines / P. Lala ; A. Walker
Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines / S. Goswami ; A. Chanda ; D. Choudhury
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis / B. Sikdar ; S. Roy ; D. Das
On-line Testing and Fault Injection / Session 5C:
Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal
Control-Flow Checking via Regular Expressions / L. Tagliaferri
FPGA-Based Fault Injection for Microprocessor Systems / P. Civera ; L. Macchiarulo ; M. Violante
Advances in BIST / Session 6A:
A BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths / K. Yamaguchi ; H. Wada ; T. Masuzawa
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit / S. Almukhaizim ; P. Petrov
A SmartBIST Variant with Guaranteed Encoding / B. Koenemann ; C. Barnhart ; B. Keller ; T. Snethen ; O. Farnsworth ; D. Wheater
Analog Test / Session 6B:
MEMS Comb-Actuator Resonance Measurement Method Using the 2[superscript nd] Harmonics of the GND Current / Y. Takahashi
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks / Z. Guo ; X. Zhang ; J. Savir ; Y.-Q. Shi
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits / A. Halder ; A. Chatterjee
Fault Tolerance / Session 6C:
Yield Increase of VLSI after Redundancy-Repairing
An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; T. Isokawa ; N. Matsui
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes / E. Sogomonyan
Various Ideas for BIST / Session 7A:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? / I. Bayraktaroglu
Hybrid BIST Using Partially Rotational Scan / K. Ichino ; T. Asakawa ; S. Fukumoto ; K. Iwasaki
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits / N. Ganguly ; A. Karmakar ; S. Chowdhury ; P. Chaudhuri
A Microcode-Based Memory BIST Implementing Modified March Algorithm / D. Youn ; T. Kim ; S. Park
Fault Simulation for VHDL Based Test Bench and BIST Evaluation / H. Farshbaf ; M. Zolfy ; S. Mirkhani ; Z. Navabi
Analog/Mixed Signal Test / Session 7B:
Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models / B. Sahu
Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator / A. Gomes
Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters / J.-H. Tsai ; M.-J. Hsiao ; T.-Y. Chang
Verification / Session 7C:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model / C.-Y. Wang ; S.-W. Tung ; J.-Y. Jou
Framework of Timed Trace Theoretic Verification Revisited / B. Zhou ; C. Myers
Efficient Pattern-Based Verification of Connections to IP Cores / I. Polian ; W. Gunther ; B. Becker
Design Verification and Robust Design Technique for Cross-Talk Faults / B. Paul ; S.-H. Choi ; Y. Im ; K. Roy
DFT Application to Real Chips / Poster Session 1:
A Practical Logic BIST for ASIC Designs / M. Sato ; K. Tsutsumida ; T. Ikeya ; M. Kawashima
TX7901 DFT / T. Kamada
An Application of Partial Scan Techniques to a High-End System LSI Design / T. Ono ; A. Kozawa ; T. Kimura ; Y. Konno ; K. Saga
Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs / H. Hanai ; S. Yamada ; H. Mori ; E. Yamashita ; T. Funakura
High-Speed Interface Testing / M. Suzuki ; R. Shimizu ; N. Naka ; K. Nakamura
A New Inter-core Built-in-Self-Test Circuits for Tri-state Buffers in the System on a Chip / T. Kishi ; M. Ohta ; T. Taniguchi ; H. Kadota
A Flexible Logic BIST Scheme and Its Application to SoC Designs / X. Wen
Practical Ideas from Universities / Poster Session 2:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan / X. Lin
Non-exhaustive Parity Testing / S. Xu
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits / K. Shimizu ; N. Itazaki
A Low-Power LFSR Architecture / T.-C. Huang ; K.-J. Lee
Author Index
Message from the Symposium Chair
Message from the Program Chair
Message from the 10th Anniversary Committee Chair
7.

図書

図書
sponsored by IEEE Computer Society, Test Technology Technical Council and IEEE Philadelphia Section
出版情報: Washington, D.C. : International Test Conference, c2001  xiv, 1201 p. ; 29 cm
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8.

図書

図書
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxxiii, 417 p. ; 28 cm
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目次情報: 続きを見る
Foreword
Acknowledgements
Organizing Committee
Steering Committee
Program Committee
Reviewers
VTS 2000 Best Paper Award
VTS 2000 Best Tutorial Award
Test Technology Technical Council
Test Technology Education Program: Overview of Tutorials
Plenary Session
Welcome Message
Keynote Address: Staying Ahead of the Test Technology Curve / Roger W. Blethen
Program Introduction / Sreejit Chakravarty ; Andre Ivanov
Invited Presentation: Testing the Limits of System-on-Chip / Ronnie Vasishta
BIST Techniques / Session 1:
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme / A. Jas ; C. Krishna ; N. Touba
Compression Technique for Interactive BIST Application / D. Kay ; S. Mourad
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers / M. Psarakis ; D. Gizopoulos ; A. Paschalis ; N. Kranitis ; Y. Zorian
Diagnosis Methods / Session 2:
Diagnosis of Tunneling Opens / J. Li ; E. McCluskey
On Diagnosing Path Delay Faults in an At-Speed Environment / R. Tekumalla ; S. Venkataraman ; J. Ghosh-Dastidar
On Improving the Accuracy Of Multiple Defect Diagnosis / S.-Y. Huang
Test Data Compression / Session 3:
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression / A. Chandra ; K. Chakrabarty
Design of Parameterizable Error-Propagating Space Compactors for Response Observation / A. Morosov ; M. Gossel ; B. Bhattacharya
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip / A. El-Maleh ; S. al Zahir ; E. Khan
Sythesis and Design for Testability / Session 4:
Testable Sequential Circuit Design: A Partition and Resynthesis Approach / R. Chou ; K. Saluja
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency / M. Nummer ; M. Sachdev
Breaking Correlation to Improve Testability / K. Ockunzzi ; C. Papachristou
Scan Chain Design / Session 5:
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals / D. Xiang ; Y. Xu
Multiple Scan Chain Design for Two-Pattern Testing / I. Polian ; B. Becker
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester / D. Bhavsar
Innovative Measurement Techniques / Session 6:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals / T. Yamaguchi ; M. Soma ; D. Halter ; R. Raina ; J. Nissen ; M. Ishida
Built-in-Chip Testing of Voltage Overshoots in High-Speed SoCs / A. Attarha ; M. Nourani
Current Measurement for Dynamic Idd Test / X. Sun ; B. Vinnakota
Diagnosis and Verification ATPG / Session 7:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction / M. Amyeen ; W. Fuchs ; I. Pomeranz ; V. Boppana
Semi-Formal Test Generation for a Block of Industrial DSP / J. Dushina ; M. Benjamin ; D. Geist
Defect Analysis and IDDx Diagnosis / Session 8:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT / A. Zenteno ; V. Champac
A Process and Technology-Tolerant I[subscript DDQ] Method for IC Diagnosis / C. Patel ; J. Plusquellic
Panel / Special Session 1:
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue
Hot Topic Session / Special Session 2:
ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing
SOC Testing / Session 9:
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment / T. Tan ; C. Lee
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
High-Level Crosstalk Defect Simulation for System-on-Chip Interconnects / X. Bai ; S. Dey
Online Testing / Session 10:
Design Diversity for Concurrent Error Detection in Sequential Logic Circuits / S. Mitra
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging / E. Sogomonyan ; A. Singh ; J. Rzeha
Design of Redundant Systems Protected against Common-Mode Failures
Self-Test Techniques / Session 11:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs / J.-R. Huang ; M. Iyer ; K.-T. Cheng
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses / W.-C. Lai
Electrically Induced Stimuli for MEMS Self-Test / B. Charlot ; S. Mir ; F. Parrain ; B. Courtois
Memory Testing / Session 12:
Flash Memory Disturbances: Modeling and Test / M. Mohammad
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories / K.-L. Cheng ; M.-F. Tsai ; C.-W. Wu
An Efficient Methodology for Generating Optimal and Uniform March Tests / S. Al-Harbi ; S. Gupta
Scalable Fault Simulation, Model Build and ATPG Methods / Session 13:
RT-Level Fault Simulation Based on Symbolic Propagation / O. Sinanoglu ; A. Orailoglu
Efficient Transparency Extraction and Utilization in Hierarchical Test / Y. Makris ; V. Patel
Analysis of Testing Methodologies for Custom Designs in PowerPC[superscript TM] Microprocessor / M. Abadir ; J. Zhu ; L.-C. Wang
Test Stimulus Generation for Analog Testing / Session 14:
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization / Y.-T. Chen ; C. Su
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications / F. Azais ; S. Bernard ; Y. Bertrand ; X. Michel ; M. Renovell
Self-Testable Pipelined ADC with Low Hardware Overhead / E. Peralias ; G. Huertas ; A. Rueda ; J. Huertas
Soft Errors and Tolerance for Soft Errors / Special Session 3:
Embedded Tutorial / Special Session 4:
Yield Optimization and Its Relation to Test
ATPG for Design Errors--Is It Possible? / Special Session 5:
Memory Diagnosis / Session 15:
Defect Oriented Fault Diagnosis for Semiconductor Memories Using Charge Analysis, Theory and Experiments / I. de Paul ; M. Rosales ; B. Alorda ; J. Segura ; C. Hawkins ; J. Soden
Enabling Embedded Memory Diagnosis via Test Response Compression / J. Chen ; J. Rajski ; J. Khare ; O. Kebichi ; W. Maly
Automatic Generation of Diagnostic March Tests / D. Niggemeyer ; E. Rudnick
Minimizing Test Power / Session 16:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator / P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch ; H.-J. Wunderlich
Test Scheduling for Minimal Energy Consumption under Power Constraints / T. Schuele ; A. Stroele
Reducing Power Dissipation during Test Using Scan Chain Disable / R. Sankaralingam ; B. Pouya
Estimating and Reducing Infant Mortality / Session 17:
Burn-in Failures and Local Region Yield: An Integrated Yield-Reliability Model / T. Barnett ; V. Nelson
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement / M. Khalil ; C.-L. Wey
MINVDD Testing for Weak CMOS ICs / C.-W. Tseng ; R. Chen ; P. Nigh
Novel ATPG Techniques / Session 18:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm / E. Gizdarski ; H. Fujiwara
On the Use of Fault Dominance in n-Detection Test Generation / S. Reddy
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outs / Y.-S. Chang ; M. Breuer
Test Scheduling, Leakage Estimation and Onchip Delay Measurement / Session 19:
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip / V. Iyengar
Average Leakage Current Estimation of CMOS Logic Circuits / J. de Gyvez ; E. van de Wetering
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links / J.-L. Huang
Fault Modeling and BIST Evaluation / Session 20:
Tools for the Characterization of Bipolar CML Testability / G. Monte ; B. Antaki ; S. Patenaude ; Y. Savaria ; C. Thibeault ; P. Trouborst
Testing of Dynamic Logic Circuits Based on Charge Sharing / K. Heragu ; M. Sharma ; R. Kundu ; R. Blanton
An Evaluation of Pseudo Random Testing for Detecting Real Defects / S. Davidson
Showcase / Special Session 6:
IP and Automation to Support IEEE P1500
Reliability Beyond GHz / Special Session 7:
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? / Special Session 8:
Author Index
Foreword
Acknowledgements
Organizing Committee
9.

図書

図書
editors, Yervant Zorian ... [et al.] ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  viii, 108 p. ; 28 cm
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Message from the Chairs
Conference Committee
TTTC Information
Plenary Session
Memory Design / Session 1:
A DRAM Compiler for Fully Optimized Memory Instances / G. Harling
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme / K. Kim ; K. Rho ; K. Lee
Design of an Embedded Fully-Depleted SOI SRAM / R. Sung ; J. Koob ; T. Brandon ; D. Elliott ; B. Cockburn
Memory BIST / Session 2:
A P1500 Compliant Programable BistShell for Embedded Memories / S. Koranne ; C. Wouters ; T. Waayers ; S. Kumar ; R. Beurze ; G. Visweswaran
BIST-Based Bitfail Mapping of an Embedded DRAM / B. Kessler ; J. Dreibelbis ; T. McMahon ; J. McCloy ; R. Kho
Tutorial on Soft Error in Memories / Session 3:
Special Session on Memory Yield and Manufacturability / Session 4:
Redundancy and Error Control / Session 5:
A Method to Caculate Redundancy Coverage for FLASH Memory / S. Matarrese ; L. Fasoli
An Error Control Code Scheme for Multilevel Flash Memories / S. Gregori ; O. Khouri ; R. Micheloni ; G. Torelli
An Approach for Evaluation of Redunancy Analysis Algorithms / S. Shoukourian ; V. Vardanian ; Y. Zorian
Fault Models and Multi-Port SRAM Testing / Session 6:
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests / Z. Al-Ars ; A. van de Goor
Realistic Fault Models and Test Procedures for Multi-Port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers
A Parallel Approach for Testing Multi-Port Static Random Access Memories / F. Karimi ; S. Irrinki ; T. Crosby ; F. Lombardi
Verification and Test / Session 7:
Equivalence Checking a 256MB SDRAM / S. Napper ; D. Yang
Testing Carry Logic Modules of SRAM-based FPGAs / X. Sun ; J. Xu ; P. Trouborst
Low Output Resistance Charge Pump for Flash Memory Programming / D. Soltesz
Author Index
Message from the Chairs
Conference Committee
TTTC Information
10.

図書

図書
edited by Robert Aitken ... [et al.] ; sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC), the IEEE Computer Society Technical Committee on Fault-Tolerant Computing(TCFTC)
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xii, 602 p. ; 23 cm
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