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1.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; edited by Brad L. Hutchings
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c2000  x, 348 p. ; 28 cm
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Conference Organizers
Architecture / Andre DeHonSession 1:
Design of a VLIW Compute Accelerator on the Transmogrifier-2 / L. Zhang ; Q. Wang ; D. Lewis
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems / M. Boyd ; T. Larrabee
Configuration Caching Management Techniques for Reconfigurable Computing / Z. Li ; K. Compton ; S. Hauck
Compilation 1 / Wayne LukSession 2:
A Matlab Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems / P. Banerjee ; N. Shenoy ; A. Choudhary ; C. Bachmann ; M. Haldar ; P. Joisha ; A. Jones ; A. Kanhare ; A. Nayak ; S. Periyacheri ; M. Walkden ; D. Zaretsky
Stream-Oriented FPGA Computing in the Streams-C High Level Language / M. Gokhale ; J. Stone ; J. Arnold ; M. Kalinowski
Applications 1 / Philip FreidenSession 3:
A Reconfigurable Computing Architecture for Microsensors / S. Scalera ; M. Falco ; B. Nelson
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor / K. Leung ; K. Ma ; W. Wong ; P. Leong
Customizing Graphics Applications: Techniques and Programming Interface / H. Styles ; W. Luk
Compilation 2 / Scott HauckSession 4:
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines / P. Diniz ; J. Park
A C to HDL Compiler for Pipeline Processing on FPGAs / T. Maruyama ; T. Hoshino
Cryptographic Applications / John McHenrySession 5:
High Performance DES Encryption in Virtex FPGAs Using Jbits / C. Patterson
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA / M. Leong O. Cheung ; K. Tsoi
An Adaptive Cryptographic Engine for IPSec Architectures / A. Dandalis ; V. Prasanna ; J. Rolim
Programming Tools / Brad HutchingsSession 6:
Death of the RLOC? / S. Singh
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations / P. James-Roxby ; S. Guccione
Fault Tolerance / Philip KuekesSession 7:
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration / J. Emmert ; C. Stroud ; B. Skaggs ; M. Abramovici
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities / S-Y. Yu ; N. Saxena ; E. McCluskey
Tunable Fault Tolerance for Runtime Reconfigurable Architectures / S. Sinha ; P. Kamarchik ; S. Goldstein
Wireless Applications / Tom KeanSession 8:
Synchronization in Software Radios--Carrier and Timing Recovery Using FPGAs / C. Dick ; F. Harris ; M. Rice
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems / A. Alsolaim ; J. Becker ; M. Glesner ; J. Starzyk
Applications 2 / Mike ButtsSession 9:
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware / B. Levine ; R. Taylor ; H. Schmit
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine / E. Sotiriades ; A. Dollas ; P. Athanas
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars / C. Ciressan ; E. Sanchez ; M. Rajman ; J-C. Chappelier
Applications 3 / Don BouldinSession 10:
A Reliable LZ Data Compressor on Reconfigurable Coprocessors / W-J. Huang
Evidence: An FPGA-Based System for Photon EVent IDENtification and CEntroiding / M. Alderighi ; S. D'Angelo ; G. Sechi
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware / M. Wirthlin ; S. Morrison ; P. Graham ; B. Bray
Poster Session 1
Configuration Relocation and Defragmentation for Reconfigurable Computing / J. Cooley ; S. Knol
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW / T. Yamauchi ; S. Nakaya ; T. Inuo ; N. Kajihara
Hardware Accelerator for Subgraph Isomorphism Problems / S. Ichikawa ; L. Udorn ; K. Konishi
A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios / K. Henriss ; P. Ruffer ; R. Ernst ; S. Hasenzahl
Reconfigurable Array Media Processor (RAMP) / K. Rath ; S. Tangirala ; P. Friel ; P. Bolsara ; J. Flores ; J. Wadley
Internet Connected FPGAs / H. Fallside ; M. Smith
A Reconfigurable Stochastic Model Simulator for analysis of parallel systems / O. Yamamoto ; Y. Shibata ; H. Kurosawa ; H. Amano
Poster Session 2
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device / M. Uno ; K. Furuta ; T. Fujii ; M. Motomura
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures / R. Maestre ; F. Kurdahi ; M. Fernandez ; R. Hermida ; N. Bagherzadeh ; H. Singh
A Communication Scheduling Algorithm For Multi-FPGA Systems / J. Suh ; D-I. Kang ; S. Crago
Preemptive Multitasking on FPGAs / L. Levinson ; R. Manner ; M. Sessler ; H. Simmler
BigSky--An On-Line Arithmetic Design Tool for FPGAs / A. Schneider ; R. McIlhenny ; M. Ercegovac
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings / B. Hutchings
Multiple Precision for Resource Minimization / G. Constantinides ; P. Cheung
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox / O. Mencer ; H. Hubert ; M. Morf ; M. Flynn
Poster Session 3
An FPGA-Based Array Processor for an Ionospheric-Imaging Radar / T. Tuan ; M. Figueroa ; F. Lind ; X. Zhou ; X. Diorio ; J. Sahr
Embedded Compilation for Multimedia Applications / N. Daw ; D. Strelow
Interfacing Reconfigurable Logic with a CPU / K. Walker ; M. Budiu
A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player / J. Scalera ; M. Jones
Accelerating Embedded Applications Using Dynamically Reconfigurable Hardware and Evolutionary Algorithms / J. Harkin ; T. McGinnity ; L. Maguire
Implementation of a Configurable Controller for an AC Drive Control: A Case Study / M. Imecs ; P. Bikfalvi ; S. Nedevschi ; J. Vasarhelyi
Pattern Recognition and Reconstruction on an FPGA Coprocessor Board
Poster Session 4
FCCMs and the Memory Wall / S. Derrien ; S. Rajopadhye
A C to Hardware/Software Compiler / K. Bazargan ; R. Kastner ; S. Ogrenci ; M. Sarrafzadeh
Evaluating Hardware Compilation Techniques / M. Weinhardt
Adapting Constant Multipliers in a Neural Network Implementation / B. Blodget
A Networked FPGA-Based Hardware Implementation of a Neural Network Application / H. Restrepo ; R. Hoffmann ; A. Perez-Uribe ; C. Teuscher
Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems / K. Suzuki ; M. Wang ; F. Zhao ; W. Dai
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing / T. Courtney ; R. Turner ; R. Woods
Combining Serialization and Reconfiguration for Convolver Designs / A. Derbyshire
Author Index
Conference Organizers
Architecture / Andre DeHonSession 1:
Design of a VLIW Compute Accelerator on the Transmogrifier-2 / L. Zhang ; Q. Wang ; D. Lewis
2.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; edited by Kenneth L. Pocek and Jeffrey Arnold
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1999  x, 319 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Co-Chairs and Program Committee
Tools 1 / Session 1:
Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System / J.M.P. Cardoso ; H.C. Neto
A CAD Suite for High-Performance FPGA Design / B. Hutchings ; P. Bellows ; J. Hawkins ; S. Hemmert ; B. Nelson ; M. Rytting
Formal Verification of Reconfigurable Cores / S. Singh ; C.J. Lillieroth
Network Applications / Session 2:
Transmutable Telecom System and Its Application / T. Miyazaki ; T. Murooka ; M. Katayama ; A. Takahara
Implementation and Evaluation of a Prototype Reconfigurable Router / J.R. Hess ; D.C. Lee ; S.J. Harper ; M.T. Jones ; P.M. Athanas
Compilation / Session 3:
Pipeline Vectorization for Reconfigurable Systems / M. Weinhardt ; W. Luk
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks / M.B. Gokhale ; J.M. Stone
Parallelizing Applications into Silicon / J. Babb ; M. Rinard ; C.A. Moritz ; W. Lee ; M. Frank ; R. Barua ; S. Amarasinghe
Architectures / Session 4:
Reconfigurable Elements for a Video Pipeline Processor / M.R. Piacentino ; G.S. van der Wal ; M.W. Hansen
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator / B. Kastrup ; A. Bink ; J. Hoogerbrugge
Tools 2 / Session 5:
CPR: A Configuration Profiling Tool / S. Cadambi ; S.C. Goldstein
Debugging Techniques for Dynamically Reconfigurable Hardware / N. McKay
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems / M. Vasilko ; D. Cabanis
Graphics Applications / Session 6:
Reconfigurable Computing for Augmented Reality / T.K. Lee ; J.R. Rice ; N. Shirazi ; P.Y.K. Cheung
Sepia: Scalable 3D Compositing using PCI Pamette / L. Moll ; A. Heirich ; M. Shand
Applications / Session 7:
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking / Z. Luo ; M. Martonosi ; P. Ashar
Fafner--Accelerating Nesting Problems with FPGAs / J.C. Alves ; J.C. Ferreira ; C. Albuquerque ; J.F. Oliveira ; J.S. Ferreira ; J. Silva Matos
DSP Applications / Session 8:
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing / T.J. Moeller ; D.R. Martinez
Optimizing FPGA-Based Vector Product Designs / D. Benyamin ; J. Villasenor
Run Time Systems / Session 9:
PCI-PipeRench and the SwordAPI: A System for Stream-based Reconfigurable Computing / R. Laufer ; R.R. Taylor ; H. Schmit
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor / A.A. Chien ; J.H. Byun
Implementing an API for Distributed Adaptive Computing Systems / M. Jones ; L. Scharf ; J. Scott ; C. Twaddle ; M. Yaconis ; K. Yao ; P. Athanas ; B. Schott
Arithmetic / Session 10:
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms / G. Orlando ; C. Paar
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping / M.P. Leong ; M.Y. Yeung ; C.K. Yeung ; C.W. Fu ; P.A. Heng ; P.H.W. Leong
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures / K. Bondalapati ; V.K. Prasanna
Poster Session 1
Accelerating Run-Time Reconfiguration on FCCMs / J.-P. Heron ; R.F. Woods
A Virtual Hardware Handler for RTR Systems / R. Turner ; S. Sezer
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results / E.K. Pauer ; P.D. Fiore ; J.M. Smith
Development System for FPGA-Based Digital Circuits / V. Sklyarov ; J. Fonseca ; R. Monteiro ; A. Oliveira ; A. Melo ; N. Lau ; I. Skliarova ; P. Neves ; A. Ferrari
Design of a JTAG Based Run Time Reconfigurable System / C. Cousineau ; F. Laperle ; Y. Savaria
Architectures for System-Level Applications of Adaptive Computing / C. Chen ; S. Crago ; J. Czarnaski ; M. French ; I. Hom ; T. Tho ; T. Valenti
Task-level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures / V. Srinivasan ; R. Vemuri
Enabling Automatic Module Generation for FCCM Compilers / A. Koch
Poster Session 2
ICARUS: A Dynamically Reconfigurable Computer Architecture / M. Baxter
SONIC--A Plug-In Architecture for Video Processing / S.D. Haynes ; J. Stone
A Reconfigurable Platform for Academic Purposes / C. Teuscher ; J.-O. Haenni ; F.J. Gomez ; H.F. Restrepo ; E. Sanchez
VHDL Placement Directives for Parametric IP Blocks / J. Hwang ; C. Patterson ; S. Mitra
Runlength Compression Techniques for FPGA Configurations / S. Hauck ; W.D. Wilson
Poster Session 3
Accelerating An IR Automatic Target Recognition Application with FPGAs / J. Jean ; X. Liang ; B. Drozd ; K. Tomko
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware / B. Levine ; S. Natarajan ; C. Tan ; D. Newport ; D. Bouldin
Hybrid Data/Configuration Caching for Striped FPGAs / D. Deshpande ; A.K. Somani ; A. Tyagi
On Reconfiguring Cache for Computing / H.-S. Kim
Reconfigurable Pipelines in VLIW Execution Units / R.D. Williams ; B.D. Kuebert
Fast Online Placement for Reconfigurable Computing Systems / K. Bazargan ; M. Sarrafzadeh
Poster Session 4
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor / L. Gao ; S. Shrivastava ; H. Lee ; G.E. Sobelman
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware / M. Abramovici ; J.T. de Sousa
Reducing Compilation Time of Zhong's FPGA-based SAT solver / P.K. Chan ; M.J. Boyd ; S. Goren ; K. Klenk ; V. Kodavati ; R. Kundu ; M. Margolese ; J. Sun ; K. Suzuki ; E. Thorne ; X. Wang ; J. Xu ; M. Zhu
FPGA-based Structures for On-line FFT and DCT / D. Lau ; A. Schneider ; M.D. Ercegovac
An FPGA-based Fan Beam Image Reconstruction Module / L. Maltar ; F.M.G. Franca ; V.C. Alves ; C.L. Amorim
Bezier Curve Rendering on Virtex / D. MacVicar ; R. Slous
Author Index
Co-Chairs and Program Committee
Tools 1 / Session 1:
Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System / J.M.P. Cardoso ; H.C. Neto
3.

図書

図書
[edited by Jeffrey Arnold and Kenneth L. Pocek] ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  x, 312 p. ; 28 cm
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目次情報: 続きを見る
Conference Organizers
Applications / Session 1:
A High I/O Reconfigurable Crossbar Switch / S. Young ; P. Alfke ; C. Fewer ; S. McMillan ; B. Blodget ; D. Levi
Congruential Sieves on a Reconfigurable Computer / H. A. Wake ; D. A. Buell
Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm / A. Dollas ; C. Kachris ; N. Bourbakis
Network Security / Session 2:
Implementation of a Content-Scanning Module for an Internet Firewall / J. Moscola ; J. Lockwood ; R. P. Loui ; M. Pachos
Compiling Policy Descriptions into Reconfigurable Firewall Processors / T. K. Lee ; S. Yusuf ; W. Luk ; M. Sloman ; E. Lupu ; N. Dulay
Communication Techniques / Session 3:
Compact FPGA-Based True and Pseudo Random Number Generators / K. H. Tsoi ; K. H. Leung ; P. H. W. Leong
Accelerating Bit Error Rate Testing Using a System Level Design Tool / V. Singh ; A. Root ; E. Hemphill ; N. Shirazi ; J. Hwang
A Hardware Gaussian Noise Generator for Channel Code Evaluation / D.-U Lee ; J. Villasenor ; P. Y. K. Cheung
Arithmetic / Session 4:
Perturbation Analysis for Word-Length Optimization / G. A. Constantinides
Improved Small Multiplier Based Multiplication, Squaring and Division / B. R. Lee ; N. Burgess
Device Architecture / Session 5:
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable / B. A. Levine ; H. H. Schmit
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development / K. Eguro ; S. Hauck
Asynchronous PipeRench: Architecture and Performance Estimations / H. Kagotani ; H. Schmit
Fault Modeling and Recovery / Session 6:
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets / M. Wirthlin ; E. Johnson ; N. Rollins ; M. Caffrey ; P. Graham
Adaptive Fault Recovery for Networked Reconfigurable Systems / W. Xu ; R. Ramanarayanan ; R. Tessier
Gamma-Ray Pulsar Detection Using Reconfigurable Computing Hardware / J. Frigo ; D. Palmer ; M. Gokhale ; M. Popkin-PaineSession 7:
Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on EPGA / A. Benkrid ; K. Benkrid ; D. Crookes
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines / H. Quinn ; L. A. Smith King ; M. Leeser ; W. Meleis
Floating Point Unit Generation and Evaluation for FPGAs / J. Liang ; O. MencerSession 8:
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs / X. Wang ; B. E. Nelson
Programming Frameworks / Session 9:
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-Based Data Structures / P. C. Diniz ; J. Park
Simulation and Synthesis of CSP-Based Interprocess Communication / P. A. Jackson ; B. L. Hutchings ; J. L. Tripp
Source Level Debugger for the Sea Cucumber Synthesizing Compiler / K. S. Hemmert
Compilation Techniques / Session 10:
Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications / J. Ou ; S. Choi ; V. K. Prasanna
Reconfigurable Computing Application Frameworks / A. L. Slade
Posters
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design / P. Banerjee ; D. Bagchi ; M. Haldar ; A. Nayak ; V. Kim ; R. Uribe
Fast Reconfiguration through Difference Compression / I. Kennedy
FPGA-Based SIMD Processor / S. Y. C. Li ; G. C. K. Cheuk ; K. H. Lee
Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview / J. P. Durbano ; F. E. Ortiz ; J. R. Humphrey ; D. W. Prather ; M. S. Mirotznik
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing / C. Toal ; S. Sezer ; X. Yu
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs
Reconfigurable High Resolution Network Camera / A. Filippov
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms / J. Resano ; D. Verkest ; D. Mozos ; S. Vernalde ; F. Catthoor
A Logic Based Hardware Development Environment / S. Belkacemi
Standarizing the Performance Assessment of Reconfigurable Processor Architectures / L. Shannon ; P. Chow
An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs / A. Jones
A Configurable Network Protocol for Cluster Based Communications Using Modular Hardware Primitives on an Intelligent NIC / R. G. Jaganathan ; K. D. Underwood ; R. Sass
Fabric-Based Systems: Model, Tools, Applications / C. Wolinski ; K. McCabe
An Estimation and Simulation Framework for Energy Efficient Design Using Platform FPGAs / S. Mohanty
Exploiting Reconfigurable Hardware for Network Security / S. Li ; J. Torresen ; O. Sorassen
A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons / K. Papademetriou ; S. Sotiropoulos
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations / K. R. Shesha Shayee
Synthesis and Estimation of Memory Interfaces for FPGA-Based Reconfigurable Computing Engines
Linear Placement for Static/Dynamic Reconfiguration in JBits / V. Krishna Marreddy ; S. Noorbaloochi ; K. Bazargan
Real-Time Extensions to a C-Like Hardware Description Language / T. Todman
RSA Encryption Using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine / K. Puttegowda ; P. Athanas
Kernel Formation in Garpcc / T. Callahan
Author Index
Conference Organizers
Applications / Session 1:
A High I/O Reconfigurable Crossbar Switch / S. Young ; P. Alfke ; C. Fewer ; S. McMillan ; B. Blodget ; D. Levi
4.

図書

図書
editors, Jeffrey Arnold, Kenneth L. Pocek ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  x, 322 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Conference Organizers
Applications I / Session 1:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
A Massively Parallel RC4 Key Search Engine / K. H. Tsoi ; K. H. Lee ; P. H. W. Leong
An FPGA Implementation of Triangle Mesh Decompression / T. Mitra ; T. Chiueh
Networking I / Session 2:
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro / G. Brebner
Control and Configuration Software for a Reconfigurable Networking Hardware Platform / T. S. Sproull ; J. W. Lockwood ; D. E. Taylor
Tool I / Session 3:
Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics / M. Budiu ; M. Mishra ; A. R. Bharambe ; S. C. Goldstein
Pam-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs / O. Mencer
Coarse-Grain Pipelining on Multiple FPGA Architectures / H. Ziegler ; B. So ; M. Hall ; P. C. Diniz
Template Matching / Session 4:
FPGA-Based Template Matching Using Distance Transforms / S. Hezel ; A. Kugel ; R. Manner ; D. M. Gavrila
Reconfigurable Shape-Adaptive Template Matching Architectures / J. Gause
Networking II / Session 5:
Assisting Network Intrusion Detection with Reconfigurable Hardware / B. L. Hutchings ; R. Franklin ; D. Carver
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing / P. Bellows ; J. Flidr ; T. Lehman ; B. Schott ; K. D. Underwood
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic / G. Memik ; S. O. Memik ; W. H. Mangione-Smith
Architecture I / Session 6:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy / G. Stitt ; B. Grattan ; J. Villarreal ; F. Vahid
Queue Machines: Hardware Compilation in Hardware / H. Schmit ; B. Levine ; B. Ylvisaker
Applications II / Session 7:
Custom Computing Machines for the Set Covering Problem / C. Plessl ; M. Platzner
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing / B. Carrion Schafer ; S. F. Quigley ; A. H. C. Chan
Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations / G. Lienhart
Architecture II / Session 8:
Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics / R. Yan
Hardware-Assisted Fast Routing / A. DeHon ; R. Huang ; J. Wawrzynek
Tools II / Session 9:
Optimum Wordlength Allocation / G. A. Constantinides
Precis: A Design-Time Precision Analysis Tool / M. L. Chang ; S. Hauck
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems / D. Kulkarni ; W. A. Najjar ; R. Rinker ; F. J. Kurdahi
Image Compression / Session 10:
Hyperspectral Image Compression on Reconfigurable Platforms / T. W. Fry
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64 / M. Sima ; S. Cotofana ; S. Vassiliadis ; J. T. J. van Eijndhoven ; K. Vissers
On Sparse Matrix-Vector Multiplication with FPGA-Based System / H. ElGindy ; Y.-L. ShuePoster Session 1:
Implementing a Simple Continuous Speech Recognition System on an FPGA / S. J. Melnikoff ; M. J. Russell
RACER--A Rapid Prototyping Accelerator for Pulsed Neural Networks / C. Grassmann ; J. K. Anlauf
Accelerating Radiosity Calculations Using Reconfigurable Platforms / H. Styles
On Implementing a Configware/Software SAT Solver / N. A. Reis ; J. T. de Sousa
Reconfigurable Object Detection in FLIR Image Sequences / J. E. Scalera ; C. F. Jones III ; M. Soni ; M. B. Bucciero ; P. M. Athanas ; A. L. Abbott ; A. Mishra
TCP-Stream Reassembly and State Tracking in Hardware / M. Necker ; D. Contis ; D. Schimmel
Fast and Guaranteed C Compilation onto the PACT-XPP Reconfigurable Computing Platform / J. M. P. Cardoso ; M. WeinhardtPoster Session 2:
Module Generators Driving the Compilation for Adaptive Computing Systems / A. Koch ; N. Kasprzyk
System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems / T. Rissa ; M. Vasilko ; J. Niittylahti
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign / T. Wiangtong
Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays / J. G. Nash
Compiling ATR Probing Codes for Execution on FPGA Hardware / W. Bohm ; R. Beveridge ; B. Draper ; C. Ross ; M. Chawathe ; W. Najjar
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks / N. Weaver
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing / T. Yokota ; M. Nagafuchi ; Y. Mekada ; T. Yoshinaga ; K. Ootsu ; T. BabaPoster Session 3:
The Design of the Amalgam Reconfigurable Cluster / J. D. Walstrom ; J. J. Cook ; D. B. Gottlieb ; S. Ferrera ; C.-W. Wang ; N. P. Carter
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor
Customising Floating-Point Designs / A. A. Gaffar ; N. ShiraziPoster Session 4:
Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes / T. Courtney ; R. Turner ; R. Woods
Author Index
Conference Organizers
Applications I / Session 1:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform / W. J. C. Melis ; P. Y. K. Cheung ; W. Luk
5.

図書

図書
[edited by Jeffrey Arnold and Kenneth L. Pocek] ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  x, 346 p. ; 28 cm
所蔵情報: loading…
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