| Message from the General Co-Chairs |
| Message from the Program Chair |
| Organizing Committee |
| Program Committee |
| List of Referees |
| Keynote Address I |
| Relaxing Constraints: Thoughts on the Evolution of Computer Architecture / Joel Emer ; Compaq Computer Corporation |
| System Architecture Tradeoffs / Session 1： |
| Impact of Chip-Level Integration on Performance of OLTP Workloads / L. Barroso ; K. Gharachorloo ; A. Nowatzyk ; B. Verghese |
| Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration / J. Torrellas ; L. Yang ; A-T. Nguyen |
| Impact of Heterogeneity on DSM Performance / R. Figueiredo ; J. Fortes |
| Memory and Cache / Session 2a： |
| Design of a Parallel Vector Access Unit for SDRAM Memory Systems / B. Mathew ; S. McKee ; J. Carter ; A. Davis |
| Modified LRU Policies for Improving Second-Level Cache Behavior / W. Wong ; J-L. Baer |
| eXtended Block Cache / S. Jourdan ; L. Rappoport ; Y. Almog ; M. Erez ; A. Yoaz ; R. Ronen |
| Networks / Session 2b： |
| Flit-Reservation Flow Control / L-S. Peh ; W. Dally |
| Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks / R. Casado ; A. Bermudez ; F. Quiles ; J. Sanchez ; J. Duato |
| Investigating QoS Support for Traffic Mixes with the MediaWorm Router / K. Yum ; A. Vaidya ; C. Das ; A. Sivasubramaniam |
| Multithreading and Microarchitecture / Session 3a： |
| Quantifying the SMT Layout Overhead--Does SMT Pull Its Weight? / J. Burns ; J-L. Gaudiot |
| Software-Controlled Multithreading Using Informing Memory Operations / T. Mowry ; S. Ramkissoon |
| Dynamic Cluster Assignment Mechanisms / R. Canal ; J. Parcerisa ; A. Gonzalez |
| Shared Memory / Session 3b： |
| High-Throughput Coherence Controllers / A. Nanda ; M. Michael ; D. Joseph |
| Coherence Communication Prediction in Shared-Memory Multiprocessors / S. Kaxiras ; C. Young |
| Improving the Throughput of Synchronization by Insertion of Delays / R. Rajwar ; A. Kagi ; J. Goodman |
| Panel Session I |
| Impact of Interconnect on Computer Architecture / Bill Dally |
| Keynote Address II |
| 2K Papers on Caches by Y2K: Do We Need More? / Jean-Loup Baer |
| Software Techniques / Session 4： |
| On the Performance of Hand vs. Automatically Optimized Numerical Codes / M. Jimenez ; J. Llaberia ; A. Fernandez |
| Cache-Efficient Matrix Transposition / S. Chatterjee ; S. Sen |
| A Prefetching Technique for Irregular Accesses to Linked Data Structures / M. Karlsson ; F. Dahlgren ; P. Stenstrom |
| Reducing Code Size with Run-Time Decompression / C. Lefurgy ; E. Piccininni ; T. Mudge |
| Prediction I / Session 5a： |
| Decoupled Value Prediction on Trace Processors / S-J. Lee ; Y. Wang ; P-C. Yew |
| Branch Transition Rate: A New Metric for Improved Branch Classification Analysis / M. Haungs ; P. Sallee ; M. Farrens |
| Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing / H. Patil ; J. Emer |
| Parallel Systems / Session 5b： |
| The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing / R. Stets ; S. Dwarkadas ; L. Kontothanassis ; U. Rencuzogullari ; M. Scott |
| PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620 / P. Behr ; S. Pletner ; A. Sodan |
| A DSM Architecture for a Parallel Computer Cenju-4 / T. Hosomi ; Y. Kanoh ; M. Nakamura ; T. Hirose |
| Prediction II / Session 6a： |
| Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors / A. Moshovos ; G. Sohi |
| A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks / H. Neefs ; H. Vandierendonck ; K. De Bosschere |
| Trace Cache Redundancy: Red and Blue Traces / A. Ramirez ; J. Larriba-Pey ; M. Valero |
| Parallel Systems Performance / Session 6b： |
| Evaluation of Active Disks for Decision Support Databases / M. Uysal ; A. Acharya ; J. Saltz |
| Investigating the Performance of Two Programming Models for Clusters of SMP PCs / F. Cappello ; O. Richard ; D. Etiemble |
| Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study / R. Bosch ; C. Stolte ; G. Stoll ; M. Rosenblum ; P. Hanrahan |
| Special Session |
| Work-in-progress / Sally McKee |
| Keynote Address III |
| Networking at Home--Directions in Connected Computing for the Consumer / Kevin Kahn |
| Novel Architecture Issues / Session 7： |
| Register Organization for Media Processing / S. Rixner ; B. Khailany ; P. Mattson ; U. Kapasi ; J. Owens |
| Architectural Issues in Java Runtime Systems / R. Radhakrishnan ; N. Vijaykrishnan ; L. John |
| The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches / A. Vartanian ; J-L. Bechennec ; N. Drach-Temam |
| Cache Memory Design for Network Processors / T-C. Chiueh ; P. Pradhan |
| Workshop Overviews |
| 4th Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC) |
| 4th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) |
| 4th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC) |
| 2nd Workshop on Parallel Computing for Irregular Applications (WPCIA2) |
| 3rd Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW) |
| Tutorial on Performance Modeling Using Hardware Counters |
| Author Index |
| Message from the General Co-Chairs |
| Message from the Program Chair |
| Organizing Committee |
図書
