SOC design methodologies : IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France

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SOC design methodologies : IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France / edited by Michel Robert ... [et al.]

資料種別:

図書

出版情報:

Boston : Kluwer Academic Publishers, c2002

形態:

xvi, 477 p. ; 24 cm

シリーズ名:

The International Federation for Information Processing ; 90 <BA39641980>

著者名:

ISBN:

9781402071485 [1402071485]

書誌ID:

BA58986877

子書誌情報

フルテキスト

所蔵情報

他の版・巻

書誌詳細

注記:

Includes bibliographical references and indexes

主題:

Embedded computer systems--Congresses; Integrated circuits--Very large scale integration--Congresses; Systems on a chip--Congresses

言語:

英語

目次情報:

Preface

Conference Committees

Architecture for Signal & Image Processing

Two ASIC for Low and Middle Levels of Real Time Image Processing / P. Lamaty ; B. Mazar ; D. Demigny ; L. Kessal ; M. Karabernou

64 x 64 Pixels General Purpose Digital Vision Chip / T. Komuro ; M. Ishikawa

A Vision System on Chip for Industrial Control / E. Senn ; E. Martin

Fast Recursive Implementation of the Gaussian Filter / J. Pons

Dynamically Re-configurable Architectures

A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals / R. David ; D. Chillet ; S. Pillement ; O. Sentieys

Dynamically Reconfigurable Architectures for Digital Signal Processing Applications / G. Sassatelli ; L. Torres ; P. Benoit ; G. Cambon ; M. Robert ; J. Galy

Reconfigurable Architecture Using High Speed FPGA / R. Bourguiba ; N. Boudouani

CAD Tools

Design Technology for Systems-on-Chip / R. Campsano ; D. MacMillen

Distributed Collaborative Design over Cave2 Framework / L. S. Indrusiak ; J. Becker ; M. Glesner ; R. Reis

High Performance Java Hardware Engine and Software Kernel for Embedded Systems / M. H. Miki ; M. Kimura ; T. Onoye ; I. Shirakawa

An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures / J. C. Otero ; F. R. Wagner

Interconnect Capacitance Modelling in a VDSM CMOS Technology / D. Bernard ; C. Landrault ; P. Nouet

IP Design & Reuse

Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design / C. Araujo ; E. Barros

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms / G. Ascia ; V. Catania ; M. Palesi

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 [mu]m Bulk and Silicon-On-Insulator CMOS Technologies / A. Neve ; D. Flandre

High Level Design Methodologies

A Standardized Co-simulation Backbone / B. A. De Mello

Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory / S. Meftali ; F. Gharsalli ; F. Rousseau ; A. A. Jerraya

Power Issues

Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model / C.H. Gebotys ; R. Muresan

Power Consumption Model for the DSP OAK Processor / P. Guitton-Ouhamou ; C. Belleudy ; M. Auguin

Design for Specific Constraints

Integration of Robustness in the Design of a Cell / J.M. Dutertre ; F.M. Roche ; G. Cathebras

Impact of Technology Spreading on MEMS design Robustness / V. Beroulle ; L. Latorre ; M. Dardalhon ; C. Oudea ; G. Perez ; F. Pressecq

Architectures

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation / N. Roma ; L. Sousa

Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder / S. M. Pisuk ; P. H. Wu

Low Power, Low Voltage

Low-Voltage Embedded-RAM Technology: Present and Future / K. Itoh ; H. Mizuno

Low-Voltage 0,25 [mu]m CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors / B. Curran ; M. Gifaldi ; J. Martin ; A. Buyuktosunoglu ; M. Margala ; D. Albonesi

Gate Sizing for Low Power Design / P. Maurine ; N. Azemard ; D. Auvergne

Timing Issues

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems / J-B. Rigaud ; J. Quartana ; L. Fesquet ; M. Renaudin

Feasible Delay Bound Definition / M. Aline

Advance in Mixed Signal

CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors / J. H. Choi ; S. Bampi

A VHDL-AMS Case Study: The Incremental Design of an Efficient 3[superscript rd] Generation MOS Model of a Deep Sub Micron Transistor / C. Lallement ; F. Pecheux ; Y. Herve

Verification & Validation

Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths / P. Johannsen ; R. Drechsler

Functional Test Generation using Constraint Logic Programming / Z. Zeng ; M. Ciesielski ; B. Rouzeyre

Test

An Industrial Approach to Core-Based System Chip Testing / E. J. Marinissen

Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme / M-L. Flottes ; J. Pouget

Random Adjacent Sequences: An Efficient Solution for Logic BIST / P. Girard ; S. Pravossoudovitch ; A. Virazel

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST / F. Azais ; S. Bernard ; Y. Bertrand ; M. Renovell

Built-in Test of Analog Non-Linear Circuits in a SOC Environment / L. Carro ; A. C. Nacul ; D. Janner ; M. Lubaszewski

Sensors

Design of a Fast CMOS APS Imager for High Speed Laser Detections / B. Casadei ; J. P. Le Normand ; Y. Hu ; B. Cunin

Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing

Authors Index

Keywords Index

Preface

Conference Committees

Architecture for Signal & Image Processing

Two ASIC for Low and Middle Levels of Real Time Image Processing / P. Lamaty ; B. Mazar ; D. Demigny ; L. Kessal ; M. Karabernou

64 x 64 Pixels General Purpose Digital Vision Chip / T. Komuro ; M. Ishikawa

A Vision System on Chip for Industrial Control / E. Senn ; E. Martin

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