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1.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Massachusetts, Boston
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xi, 289 p. ; 28 cm
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Message from the General Chair
Message from the Program Committee
Reviewers
Invited Talk
Equations in the Algebra of Logic / S. Rudeanu
Algebra I
Some Results on the Centralizers of Monoids in Clone Theory / H. Machida ; I. Rosenberg ; M. Miyakawa
Partial Hyperclones on a Finite Set / B. Romov
On the Structures of Weak Interlaced Bilattice / M. Kondo
Logical Design I
Improving the Characterization of p-Valued Threshold Functions / C. Moraga
A Conjunctive Canonical Expansion of Multiple-Valued Functions / E. Dubrova ; P. Farm
Sierpinski Gaskets for Logic Functions Representation / D. Popel ; A. Dani
Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals / N. Takagi ; K. Nakashima
Circuits I
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI / Y. Yuminaka ; T. Morishita ; T. Aoki ; T. Higuchi
An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator / T. Waho ; S. Kobayashi ; K. Matsuura
Voltage Comparator Circuits for Multiple-Valued CMOS Logic / Y. Guo ; K. Current
Logical Design II
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions / D. Jankovic ; R. Stankovic ; R. Drechsler
Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results / K. Adams ; J. McGregor
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection / B. Polianskikh ; Z. Zilic
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis / M. Natsui
Consequence and Complexity in Infinite-Valued Logic: A Survey / V. Marra ; D. Mundici
Spectral Techniques
Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams / J. Astola
Chrestenson Spectrum Computation Using Cayley Color Graphs / M. Thornton ; D. Miller ; W. Townsend
The Role of Super-Fast Transforms in Speeding Up Quantum Computations / K. Radecka
Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images / B. Falkowski ; B. Olejnicka
Circuits II
Design of Dynamic Reliability Indices / E. Zaitseva ; V. Levashenko
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits / N. Kamiura ; T. Isokawa ; N. Matsui
Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics / X. Wu ; P. Wang ; Y. Xia
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition / H. Kimura ; T. Hanyu ; M. Kameyama
Optimization of Multi-Valued Multi-Level Networks / M. Gao ; J. Jiang ; Y. Jiang ; Y. Li ; A. Mishchenko ; S. Sinha ; T. Villa ; R. Brayton
Algebra II
de Morgan Bisemilattice of Fuzzy Truth Value / H. Kikuchi
Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra / T. Ninomiya ; M. Mukaidono
On Functions Defined on Free Boolean Algebras / D. Simovici ; S. Jaroszewicz
Logical Design III
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 1: LAR Based Model / S. Yanushkevich ; P. Dziurzanski ; V. Shmerko
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 2: LWL Based Model / A. Tomaszewska
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics / I. Polian ; P. Engelke ; B. Becker
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms
Decision Diagrams
Variable Selection Heuristics and Optimum Decision Trees--An Experimental Study / N. Otsu
On the Construction of Multiple-Valued Decision Diagrams
Evaluation of Static Variable Ordering Heuristics for MDD Construction
Representations of Logic Functions Using QRMDDs / S. Nagayama ; T. Sasao ; Y. Iguchi ; M. Matsuura
Circuits III
Fully Source-Coupled Logic Based Multiple-Valued VLSI / T. Ike
A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block / S. Han ; S. Park ; H. Seong ; H. Kim
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits / M. Inaba ; K. Tanno ; O. Ishizuka
Author Index
Message from the General Chair
Message from the Program Committee
Reviewers
2.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Institute of Computer Science Polish Academy of Sciences
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 380 p. ; 28 cm
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Preface
Symposium Organizers and Program Committee
Referees
Invited Address / Session 1:
Algebras for Hazard Detection / J. Brzozowski ; Z. Esik ; Y. Iland
Circuits I / Session 2a:
A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits / M. Abd-El-Barr ; A. Al-Mutawa
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources / T. Ike ; T. Hanyu ; M. Kameyama
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators / M. Inaba ; K. Tanno ; O. Ishizuka
Design and Verification of Systems / Session 2b:
An Application of Multiple-Valued Logic to Test Case Generation for Software System Functional Testing / M. Hu
Spectral Techniques in Binary and Multiple-Valued Switching Theory / M. Karpovsky ; R. Stankovic ; C. Moraga
Tunnelling Diode Technology / W. Prost ; U. Auer ; F-J. Tegude ; C. Pacha ; K. Goser ; R. Duschl ; K. Eberl ; O. SchmidtSession 3:
Circuits II / Session 4a:
Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology / I. Ben Dhaou ; E. Dubrova ; H. Tenhunen
A 4-Digit CMOS Quaternary to Analog Converter with Current Switch and Neuron MOS Down-Literal Circuit / S. Han ; Y. Choi ; H. Kim
Fuzzy Logics and Their Applications I / Session 4b:
On Some Classes of Fuzzy Information Relations / A. Radzikowska ; E. Kerre
On Complete Residuated Many-Valued Logics with T-Norm Conjunction / F. Esteva ; L. Godo
Circuits III / Session 5a:
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors / T. Uemura ; T. Baba
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-Valued Circuits / T. Waho ; K. Hattori ; Y. Takamatsu
The Use of Arithmetic Operators in a Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Architecture / H. Teng ; R. Bolton
Fuzzy Logics and Their Applications II / Session 5b:
Evaluation of Inconsistency in a 2-Way Fuzzy Adaptive System Using Shadowed Sets / E. Gurkan ; A. Erkmen ; I. Erkmen
Identification of Incompletely Specified Fuzzy Unate Logic Function / H. Kikuchi
Representation Theorems and the Semantics of (Semi)Lattice-Based Logics / V. Sofronie-StokkermansSession 6:
Tutorial / Session 7:
Tutorial: Complexity of Many-Valued Logics / R. Hahnle
Exploiting Polarity in Multiple-Valued Inference Systems / Z. StachniakSession 8:
Logic Design I / Session 9a:
Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity / A. Al-Rabadi ; M. Perkowski
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits / K. Shimabukuro ; C. Zukeran
Decomposition of Multi-Valued Functions into Min- and Max-Gates / C. Lang ; B. Steinbach
Automated Reasoning and Complexity I / Session 9b:
Cut-Elimination in a Sequents-of-Relations Calculus for Godel Logic / M. Baaz ; A. Ciabattoni ; C. Fermuller
Model Checking with Multi-Valued Temporal Logics / M. Chechik ; S. Easterbrook ; B. Devereux
Automated Reasoning with Ordinary Assertions and Default Assumptions / D. Van Heule ; A. Hoogewijs
Logic Design II / Session 10a:
Information Theory Method for Flexible Network Synthesis / V. Cheushev ; S. Yanushkevich ; V. Shmerko ; J. Kolodziejczyk
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic / T. Sasao
Two-Stage Exact Detection of Symmetries / A. Tomaszewska ; P. Dziurzanski
Automated Reasoning and Complexity II / Session 10b:
A Modular Reduction of Regular Logic to Classical Logic / R. Bejar ; F. Manya
Hypersequents as a Uniform Framework for Urquhart's C, MTL and Related Logics
Polynomial-Time Algorithms for Verification of Some Properties of k-Valued Functions Represented by Polynomials / S. Selezneva
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI / Session 11:
Computing Paradigms / Session 12a:
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing / M. Hiratsuka ; T. Aoki ; T. Higuchi
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation / M. Natsui
An Axiomatization of Generalized Entropy of Partitions / D. Simovici ; S. Jaroszewicz
MV Logics and Algebras I / Session 12b:
Many Valued Paraconsistent Logic / C. Morgan
On Logical Fiberings and Decomposition of Many-Valued Operations: A Brief Survey / J. Pfalzgraf
Relations between Clones and Full Monoids / H. Machida ; M. Miyakawa ; I. Rosenberg
Classical Gentzen-Type Methods in Propositional Many-Valued Logics / A. AvronSession 13:
Decision Diagrams / Session 14a:
Selection of Efficient Re-Ordering Heuristics for MDD Construction / F. Schmiedle ; W. Gunther ; R. Drechsler
Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies / M. Stankovic ; J. Astola ; K. Egiazarian
Design of Haar Wavelet Transforms and Haar Spectral Transform Decision Diagrams for Multiple-Valued Functions
Fuzzy Logics and Set Theories / Session 14b:
A Set Theory within Fuzzy Logic / P. Hajek ; Z. Hanikova
On a Kleenean Extension of Fuzzy Measure / T. Araki ; M. Mukaidono ; F. Yamamoto
On Axiomatic Characterization of Fuzzy Approximation Operators II. The Rough Fuzzy Set Based Case / H. Thiele
Neural Networks / Session 15a:
A Functional Manipulation for Improving Tolerance against Multiple-Valued Weight Faults of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; N. Matsui
Logic Circuit Diagnosis by Using Neural Networks / H. Tatsumi ; Y. Murai ; S. Tokumasu
The Designing and Training of a Fuzzy Neural Hamming Classifier / Q. Hua ; Q-L. Zhen
MV Logics and Algebras II / Session 15b:
Weierstrass Approximations by Lukasiewicz Formulas with One Quantified Variable / S. Aguzzoli ; D. Mundici
Composing Submonads / P. Eklund ; M. Galan ; J. Medina ; M. Ojeda-Aciego ; A. Valverde
A Method of Uncertainty Reasoning by Using Information / J. Ma ; J. Liu ; Y. Xu
Author Index
Preface
Symposium Organizers and Program Committee
Referees
3.

図書

図書
[sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Toronto, Altera Corporation]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  xiv, 353 p. ; 28 cm
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4.

図書

図書
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Silver Spring, MD : IEEE Computer Society Press, c1983  xii, 431 p. ; 28 cm
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5.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xiv, 302 p. ; 28 cm
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6.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Japanese Research Group on Multiple-Valued Logic, Meiji University
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xiv, 398 p. ; 28 cm
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目次情報: 続きを見る
Message from the Symposium Chair
Message from the Program Committee
Symposium Committee
Referees
Invited Address / Session 1:
Fuzzy Logic as a Basis for a Theory of Hierarchical Definability (THD) / L. Zadeh
Logic Design I / Session 2A:
Implementation of Multiple-Valued Functions Using Literal-Splitting Technique / E. Dubrova
Hyperoperations on {0, 1, 2} Based on Min, Max, and Universal Literal Operations / N. Takagi ; K. Nakashima
An Extension of Ternary Majority Function and Its Application to Evolvable System / Y. Yamamoto
A New Construction of the Irreducible Polynomial for Parallel Multiplier over GF(2[superscript m]) / J.-H. Hwang ; K.-J. Moon ; S.-Y. Park ; H.-S. Kim
Functional Expressions / Session 2B:
New Information on the Effectiveness of Different Reed-Muller Algebras on the Representation of Quaternary Functions / K. Adams ; J. McGregor
Polynomial Expansions over GF(3) Based on Fastest Transformation / B. Falkowski ; C. Fu
The Generation Circulation Method to Generalized Reed-Muller Coefficients over GF(3) / C. Lee ; G.-Y. Byun ; B.-S. Shin ; J.-H. Sim
Optimization of GF(4) Expressions Using the Extended Dual Polarity Property / D. Jankovic ; R. Stankovic ; C. Moraga
Fuzzy Logic / Session 3A:
Normal Forms for Fuzzy Logic Functions / I. Perfilieva
Towards Fuzzy Type Theory / V. Novak
Universes of Fuzzy Sets--A Short Survey / S. Gottwald
Fixed Points for Fuzzy Rule Bases and Fuzzy Chaining Syllogism / K. Soleimani ; M. Mashinchi ; H. Maleki
Automated Finding of the Willis Ring in MR Angiography Images Using Fuzzy Knowledge Base / S. Kobashi ; K. Kondo ; Y. Hata
LSI Design / Session 3B:
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms / J. Sakiyama ; T. Aoki ; T. Higuchi
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic / T. Hanyu ; T. Takahashi ; M. Kameyama
MVL Circuit Design and Characterization at the Transistor Level Using SUS-LOC / E. Kinvi-Boh ; M. Aline ; O. Sentieys ; E. Olson
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-valued Multiple-Output Logic Circuits / H. Babu ; Md. R. Islam ; A. Ali ; Md. M. Akon ; Md. A. Rahaman ; Md. F. Islam
Recursive Evaluation of the Generalized Reed-Muller Coefficients / G. Na ; S. Kim ; J. Choi ; H. Kim
Logic Design II / Session 4A:
Cascade Realizations of Two-Valued Input Multiple-Valued Output Functions Using Decomposition of Group Functions / T. Sasao
A Novel Technology Mapping Method for AND/XOR Expressions / S.-B. Ko ; J.-C. Lo
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space / A. Al-Rabadi
Multi-output Galois Field Sum of Products Synthesis with New Quantum Cascades / M. Khan ; M. Perkowski ; P. Kerntopf
Relationship between UCHT and FFT / S. Xie ; S. Rahardja ; Z. Gu
Logics and Algebras / Session 4B:
Several Remarks on Non-Boolean Functions over Boolean Algebras / D. Simovici
Complete and Independent Sets of Axioms of Boolean Algebra / T. Ninomiya ; M. Mukaidono
Characterization of the Axiomatizable Prenex Fragments of First-Order Godel Logics / M. Baaz ; N. Preining ; R. Zach
New Logical and Complexity Results for Signed-SAT / C. Ansotegui ; F. Manya
From Intuitionistic Logic to Godel-Dummett Logic via Parallel Dialogue Games / C. Fermuller ; A. Ciabattoni
Biomorphic Analog Devices Based on Reaction-Diffusion Systems / T. Asai ; Y. AmemiyaSession 5:
LSI Circuits / Session 6A:
Multiple-Valued Dynamic Source-Coupled Logic / A. Mochizuki
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic / K. Degawa
A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator / S. Han ; Y. Choi ; H. Seong
A Novel Multiple-Input Multiple-Valued Semi-floating-gate Latch / O. Mirmotahari ; Y. Berg
Decision Diagrams I / Session 6B:
On the Size of Multiple-Valued Decision Diagrams / D. Miller ; G. Dueck
Efficient Minimization of Multiple-Valued Decision Diagrams for Incompletely Specified Functions / D. Popel ; R. Drechsler
Compact Representations of Logic Functions Using Heterogeneous MDDs / S. Nagayama
Complexity of Decision Trees for Boolean Functions / R. Freivalds ; M. Miyakawa ; I. Rosenberg
Nano Technology / Session 7A:
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic / H. Inokawa ; Y. Takahashi
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-valued Logic / K.-W. Song ; S. Lee ; D. Kim ; K. Kim ; J. Kyung ; G. Baek ; C.-A. Lee ; J. Lee ; B.-G. Park
Proposal of Four-Valued MRAM Based on MTJ/RTD Structure / T. Uemura ; M. Yamamoto
Modeling and Simulation / Session 7B:
Modeling Multi-valued Circuits in SystemC / D. Grosse ; G. Fey
Dynamic Reliability Indices for Multi-state System / E. Zaitseva
CTL Model-Checking over Logics with Non-classical Negations / M. Chechik ; W. MacCaull
Clone Theory / Session 8A:
On the Centralizers of Monoids in Clone Theory / H. Machida
Generation of the Post Lattice by Irreducible Clones / G. Pogosyan
On Intervals of Partial Clones of Boolean Partial Functions / L. Haddad ; G. Simons
Spectral Techniques / Session 8B:
Family of Fast Transforms over GF(3) Logic
Spectral Transforms of Mixed-Radix MVL Functions / M. Thornton
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation / R. Krenz ; A. Kuehlmann
Functions of Multiple-Valued Logic and the Complexity of Constraint Satisfaction: A Short Survey / A. Krokhin ; A. Bulatov ; P. JeavonsSession 9:
Applications / Session 10A:
Learning Subjective Probabilities from a Small Data Set / C. Huang
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques / S. Kinder
From Continuous to Multiple-Valued Data
Decision Diagrams II / Session 10B:
Augmented Sifting of Multiple-Valued Decision Diagrams
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions / J. Butler
Generalized Complex Spectral Decision Diagrams Using Unified Complex Hadamard Transform
Author Index
Message from the Symposium Chair
Message from the Program Committee
Symposium Committee
7.

図書

図書
International Symposium on Multiple-Valued Logic
出版情報: [s.l.] : IEEE, 1978  v, 298 p. ; 28 cm
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8.

図書

図書
International Symposium on Multiple-Valued Logic
出版情報: [s.l.] : IEEE, c1976  vii, 272 p. ; 28 cm
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9.

図書

図書
sponsoring organizations, IEEE, IEEE Computer Society, the University of Oklahoma
出版情報: New York, NY : the Institute of Electrical and Electronics Engineers, Inc., c1981 , Los Angeles, CA : Order from IEEE Computer Society , Piscataway, NJ : Order from IEEE Service Center  vi, 298 p. ; 28 cm
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10.

図書

図書
International Symposium on Multiple-Valued Logic
出版情報: Silver Spring : IEEE Computer Society Press, c1982  x, 341 p. ; 28 cm
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