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1.

図書

図書
Andrew S. Tanenbaum
出版情報: Upper Saddle River, N.J. : Prentice Hall, c2001  xxiv, 951 p. ; 25 cm
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2.

図書

図書
Andrew S. Tanenbaum and David J. Wetherall
出版情報: Boston ; Tokyo : Pearson Education, c2011  951 p. ; 24 cm
シリーズ名: Pearson international edition
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3.

図書

図書
A・S・タネンバウム著 ; 水野忠則 [ほか] 訳
出版情報: 東京 : プレンティスホール出版, 1999.5  xv, 766p ; 23cm
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4.

図書

図書
Andrew S. Tanenbaum
出版情報: Upper Saddle River, N.J. : Pearson, Prentice Hall, c2008  xxvii, 1076 p. ; 25 cm
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目次情報: 続きを見る
Introducation / 1:
What is an Operating System? / 1.1:
The Operating System as an Extended Machine / 1.1.1:
The Operating System as a Resource Manager / 1.1.2:
History of Operating Systems / 1.2:
The First Generation / 1.2.1:
The Second Generation / 1.2.2:
The Third Generation / 1.2.3:
The Fourth Generation / 1.2.4:
Computer Hardware Review / 1.3:
Processors / 1.3.1:
Memory / 1.3.2:
Disks / 1.3.3:
Tapes / 1.3.4:
I/O Devices / 1.3.5:
Buses / 1.3.6:
Booting the Computer / 1.3.7:
The Operating System Zoo / 1.4:
Mainframe Operating Systems / 1.4.1:
Server Operating Systems / 1.4.2:
Multiprocessor Operating Systems / 1.4.3:
Personal Computer Operating Systems / 1.4.4:
Handheld Computer Operating Systems / 1.4.5:
Embedded Operating Systems / 1.4.6:
Sensor Node Operating Systems / 1.4.7:
Real-Time Operating Systems / 1.4.8:
Smart Card Operating Systems / 1.4.9:
Operating System Concepts / 1.5:
Processes / 1.5.1:
Address Spaces / 1.5.2:
Files / 1.5.3:
Input/Output / 1.5.4:
Protection / 1.5.5:
The Shell / 1.5.6:
Ontogeny Recapitulates Phylogeny / 1.5.7:
System Calls / 1.6:
System Calls for Process Management / 1.6.1:
System Calls for File Management / 1.6.2:
System Calls for Directory Management / 1.6.3:
Miscellaneous System Calls / 1.6.4:
The Windows Win32 API / 1.6.5:
Operating System Structure / 1.7:
Monolithic Systems / 1.7.1:
Layered Systems / 1.7.2:
Microkernels / 1.7.3:
Client-Server Model / 1.7.4:
Virtual Machines / 1.7.5:
Exokernels / 1.7.6:
The World According to C / 1.8:
The C Language / 1.8.1:
Header Files / 1.8.2:
Large Programming Projects / 1.8.3:
The Model of Run Time / 1.8.4:
Research on Operating Systems / 1.9:
Outline of the Rest of This Book / 1.10:
Metric Units / 1.11:
Summary / 1.12:
Processes and Threads / 2:
The Process Model / 2.1:
Process Creation / 2.1.2:
Process Termination / 2.1.3:
Process Hierarchies / 2.1.4:
Process States / 2.1.5:
Implementation of Processes / 2.1.6:
Modeling Multiprogramming / 2.1.7:
Threads / 2.2:
Thread Usage / 2.2.1:
The Classical Thread Model / 2.2.2:
Posix Threads / 2.2.3:
Implementing Threads in User Space / 2.2.4:
Implementing Threads in the Kernel / 2.2.5:
Hybrid Implementations / 2.2.6:
Scheduler Activations / 2.2.7:
Pop-Up Threads / 2.2.8:
Making Single-Threaded Code Multithreaded / 2.2.9:
Interprocess Communication / 2.3:
Race Conditions / 2.3.1:
Critical Regions / 2.3.2:
Mutual Exclusion with Busy Waiting / 2.3.3:
Sleep and Wakeup / 2.3.4:
Semaphores / 2.3.5:
Mutexes / 2.3.6:
Monitors / 2.3.7:
Message Passing / 2.3.8:
Barriers / 2.3.9:
Scheduling / 2.4:
Introduction to Scheduling / 2.4.1:
Scheduling in Batch Systems / 2.4.2:
Scheduling in Interactive Systems / 2.4.3:
Scheduling in Real-Time Systems / 2.4.4:
Policy versus Mechanism / 2.4.5:
Thread Scheduling / 2.4.6:
Classical Ipc Problems / 2.5:
The Dining Philosophers Problem / 2.5.1:
The Readers and Writers Problem / 2.5.2:
Research on Processes and Threads / 2.6:
Memory Management / 2.7:
No Memory Abstraction / 3.1:
A Memory Abstraction: Address Spaces / 3.2:
The Notion of an Address Space / 3.2.1:
Swapping / 3.2.2:
Managing Free Memory / 3.2.3:
Virtual Memory / 3.3:
Paging / 3.3.1:
Page Tables / 3.3.2:
Speeding Up Paging / 3.3.3:
Page Tables for Large Memories / 3.3.4:
Page Lacement Algorithms / 3.4:
The Optimal Page Replacement Algorithm / 3.4.1:
The Not Recently Used Page Replacement Algorithm / 3.4.2:
The First-In, First-Out / 3.4.3:
The Second Chance Page Replacement Algorithm / 3.4.4:
The Clock Page Replacement Algorithm / 3.4.5:
The Least Recently Used / 3.4.6:
S / 3.4.7:
Introducation / 1:
What is an Operating System? / 1.1:
The Operating System as an Extended Machine / 1.1.1:
5.

図書

図書
アンドリュー・S・タネンバウム著 ; 長尾高弘訳
出版情報: 東京 : ピアソン・エデュケーション, 2000.9  xvi, 746p ; 23cm
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6.

図書

図書
Andrew S. Tanenbaum ; with contributions from James R. Goodman
出版情報: London : Prentice Hall International , Upper Saddle River, N.J. : Prentice Hall, c1999  xviii, 669 p. ; 24 cm
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目次情報: 続きを見る
Introduction / 1:
Computer Systems Organization / 2:
The Digital Logic Level / 3:
The Microarchitecture Level / 4:
The Instruction Set Architecture Level / 5:
The Operating System Machine Level / 6:
The Assembly Language Level / 7:
Parallel Computer Architectures / 8:
Reading List and Bibliography / 9:
Binary Numbers / Appendix A:
Floating-Point Numbers / Appendix B:
Preface
Structured Computer Organization / 1.1:
Languages, Levels, and Virtual Machines / 1.1.1:
Contemporary Multilevel Machines / 1.1.2:
Evolution of Multilevel Machines / 1.1.3:
Milestones in Computer Architecture / 1.2:
The Zeroth Generation-Mechanical Computers (1642-1945) / 1.2.1:
The First Generation-Vacuum Tubes (1945-1955) / 1.2.2:
The Second Generation-Transistors (1955-1965) / 1.2.3:
The Third Generation-Integrated Circuits (1965-1980) / 1.2.4:
The Fourth Generation-Very Large Scale Integration (1980-?) / 1.2.5:
The Fifth Generation-Invisible Computers / 1.2.6:
The Computer Zoo / 1.3:
Technological and Economic Forces / 1.3.1:
The Computer Spectrum / 1.3.2:
Disposable Computers / 1.3.3:
Microcontrollers / 1.3.4:
Game Computers / 1.3.5:
Personal Computers / 1.3.6:
Servers / 1.3.7:
Collections of Workstations / 1.3.8:
Mainframes / 1.3.9:
Example Computer Families / 1.4:
Introduction to the Pentium 4 / 1.4.1:
Introduction to the UltraSPARC III / 1.4.2:
Introduction to the 8051 / 1.4.3:
Metric Units / 1.5:
Outline of This Book / 1.6:
Processors / 2.1:
CPU Organization / 2.1.1:
Instruction Execution / 2.1.2:
RISC versus CISC / 2.1.3:
Design Principles for Modern Computers / 2.1.4:
Instruction-Level Parallelism / 2.1.5:
Processor-Level Parallelism / 2.1.6:
Primary Memory / 2.2:
Bits / 2.2.1:
Memory Addresses / 2.2.2:
Byte Ordering / 2.2.3:
Error-Correcting Codes / 2.2.4:
Cache Memory / 2.2.5:
Memory Packaging and Types / 2.2.6:
Secondary Memory / 2.3:
Memory Hierarchies / 2.3.1:
Magnetic Disks / 2.3.2:
Floppy Disks / 2.3.3:
IDE Disks / 2.3.4:
SCSI Disks / 2.3.5:
RAID / 2.3.6:
CD-ROMs / 2.3.7:
CD-Recordables / 2.3.8:
CD-Rewritables / 2.3.9:
DVD / 2.3.10:
Blu-Ray / 2.3.11:
Input/Output / 2.4:
Buses / 2.4.1:
Terminals / 2.4.2:
Mice / 2.4.3:
Printers / 2.4.4:
Telecommunications Equipment / 2.4.5:
Digital Cameras / 2.4.6:
Character Codes / 2.4.7:
Summary / 2.5:
Gates and Boolean Algebra / 3.1:
Gates / 3.1.1:
Boolean Algebra / 3.1.2:
Implementation of Boolean Functions / 3.1.3:
Circuit Equivalence / 3.1.4:
Basic Digital Logic Circuits / 3.2:
Integrated Circuits / 3.2.1:
Combinational Circuits / 3.2.2:
Arithmetic Circuits / 3.2.3:
Clocks / 3.2.4:
Memory / 3.3:
Latches / 3.3.1:
Flip-Flops / 3.3.2:
Registers / 3.3.3:
Memory Organization / 3.3.4:
Memory Chips / 3.3.5:
RAMs and ROMs / 3.3.6:
CPU Chips and Buses / 3.4:
CPU Chips / 3.4.1:
Computer Buses / 3.4.2:
Bus Width / 3.4.3:
Bus Clocking / 3.4.4:
Bus Arbitration / 3.4.5:
Bus Operations / 3.4.6:
Example CPU Chips / 3.5:
The Pentium 4 / 3.5.1:
The UltraSPARC III / 3.5.2:
The 8051 / 3.5.3:
Example Buses / 3.6:
The ISA Bus / 3.6.1:
The PCI Bus / 3.6.2:
PCI Express / 3.6.3:
The Universal Serial Bus / 3.6.4:
Interfacing / 3.7:
I/O Chips / 3.7.1:
Address Decoding / 3.7.2:
An Example Microarchitecture / 3.8:
The Data Path / 4.1.1:
Microinstructions / 4.1.2:
Microinstruction Control: The Mic-1 / 4.1.3:
An Example Isa: IJVM / 4.2:
Stacks / 4.2.1:
The IJVM Memory Model / 4.2.2:
The IJVM Instruction Set / 4.2.3:
Compiling Java to IJVM / 4.2.4:
An Example Implementation / 4.3:
Microinstructions and Notation / 4.3.1:
Implementation of IJVM Using the Mic-1 / 4.3.2:
Design of the Microarchitecture Level / 4.4:
Speed versus Cost / 4.4.1:
Reducing the Execution Path Length / 4.4.2:
A Design with Prefetching: The Mic-2 / 4.4.3:
A Pipelined Design: The Mic-3 / 4.4.4:
A Seven-Stage Pipeline: The Mic-4 / 4.4.5:
Improving Performance / 4.5:
Branch Prediction / 4.5.1:
Out-of-Order Execution and Register Renaming / 4.5.3:
Speculative Execution / 4.5.4:
Examples of the Microarchitecture Level / 4.6:
The Microarchitecture of the Pentium 4 CPU / 4.6.1:
The Microarchitecture of the UltraSPARC-III Cu CPU / 4.6.2:
The Microarchitecture of the 8051 CPU / 4.6.3:
Comparison of the Pentium, Ultrasparc, and 8051 / 4.7:
Overview of the ISA Level / 4.8:
Properties of the ISA Level / 5.1.1:
Memory Models / 5.1.2:
Instructions / 5.1.3:
Overview of the Pentium 4 ISA Level / 5.1.5:
Overview of the UltraSPARC III ISA Level / 5.1.6:
Overview of the 8051 ISA Level / 5.1.7:
Data Types / 5.2:
Numeric Data Types / 5.2.1:
Nonnumeric Data Types / 5.2.2:
Data Types on the Pentium 4 / 5.2.3:
Data Types on the UltraSPARC III / 5.2.4:
Data Types on the 8051 / 5.2.5:
Instruction Formats / 5.3:
Design Criteria for Instruction Formats / 5.3.1:
Expanding Opcodes / 5.3.2:
The Pentium 4 Instruction Formats / 5.3.3:
The UltraSPARC III Instruction Formats / 5.3.4:
The 8051 Instruction Formats / 5.3.5:
Addressing / 5.4:
Addressing Modes / 5.4.1:
Immediate Addressing / 5.4.2:
Direct Addressing / 5.4.3:
Register Addressing / 5.4.4:
Register Indirect Addressing / 5.4.5:
Indexed Addressing / 5.4.6:
Based-Indexed Addressing / 5.4.7:
Stack Addressing / 5.4.8:
Addressing Modes for Branch Instructions / 5.4.9:
Orthogonality of Opcodes and Addressing Modes / 5.4.10:
The Pentium 4 Addressing Modes / 5.4.11:
The UltraSPARC III Addressing Modes / 5.4.12:
The 8051 Addressing Modes / 5.4.13:
Discussion of Addressing Modes / 5.4.14:
Instruction Types / 5.5:
Data Movement Instructions / 5.5.1:
Dyadic Operations / 5.5.2:
Monadic Operations / 5.5.3:
Comparisons and Conditional Branches / 5.5.4:
Procedure Call Instructions / 5.5.5:
Loop Control / 5.5.6:
The Pentium 4 Instructions / 5.5.7:
The UltraSPARC III Instructions / 5.5.9:
The 8051 Instructions / 5.5.10:
Comparison of Instruction Sets / 5.5.11:
Flow of Control / 5.6:
Sequential Flow of Control and Branches / 5.6.1:
Procedures / 5.6.2:
Coroutines / 5.6.3:
Traps / 5.6.5:
Interrupts
A Detailed Example: The Towers of Hanoi / 5.7:
The Towers of Hanoi in Pentium 4 Assembly Language / 5.7.1:
The Towers of Hanoi in UltraSPARC III Assembly Language / 5.7.2:
The IA-64 Architecture and the Itanium 2 / 5.8:
The Problem with the Pentium 4 / 5.8.1:
The IA-64 Model: Explicitly Parallel Instruction Computing / 5.8.2:
Reducing Memory References / 5.8.3:
Instruction Scheduling / 5.8.4:
Reducing Conditional Branches: Predication / 5.8.5:
Speculative Loads / 5.8.6:
Virtual Memory / 5.9:
Paging / 6.1.1:
Implementation of Paging / 6.1.2:
Demand Paging and the Working Set Model / 6.1.3:
Page Replacement Policy / 6.1.4:
Page Size and Fragmentation / 6.1.5:
Segmentation / 6.1.6:
Implementation of Segmentation / 6.1.7:
Virtual Memory on the Pentium 4 / 6.1.8:
Virtual Memory on the UltraSPARC III / 6.1.9:
Virtual Memory and Caching / 6.1.10:
Virtual I/O Instructions / 6.2:
Files / 6.2.1:
Implementation of Virtual I/O Instructions / 6.2.2:
Directory Management Instructions / 6.2.3:
Virtual Instructions for Parallel Processing / 6.3:
Process Creation / 6.3.1:
Race Conditions / 6.3.2:
Process Synchronization Using Semaphores / 6.3.3:
Example Operating Systems / 6.4:
Examples of Virtual Memory / 6.4.1:
Examples of Virtual I/O / 6.4.3:
Examples of Process Management / 6.4.4:
Introduction to Assembly Language / 6.5:
What Is an Assembly Language? / 7.1.1:
Why Use Assembly Language? / 7.1.2:
Format of an Assembly Language Statement / 7.1.3:
Pseudoinstructions / 7.1.4:
Macros / 7.2:
Macro Definition, Call, and Expansion / 7.2.1:
Macros with Parameters / 7.2.2:
Advanced Features / 7.2.3:
Implementation of a Macro Facility in an Assembler / 7.2.4:
The Assembly Process / 7.3:
Two-Pass Assemblers / 7.3.1:
Pass One / 7.3.2:
Pass Two / 7.3.3:
The Symbol Table / 7.3.4:
Linking and Loading / 7.4:
Tasks Performed by the Linker / 7.4.1:
Structure of an Object Module / 7.4.2:
Binding Time and Dynamic Relocation / 7.4.3:
Dynamic Linking / 7.4.4:
On-Chip Paralellism / 7.5:
On-Chip Multithreading / 8.1.1:
Single-Chip Multiprocessors / 8.1.3:
Coprocessors / 8.2:
Network Processors / 8.2.1:
Media Processors / 8.2.2:
Cryptoprocessors / 8.2.3:
Shared-Memory Multiprocessors / 8.3:
Multiprocessors vs. Multicomputers / 8.3.1:
Memory Semantics / 8.3.2:
UMA Symmetric Multiprocessor Architectures / 8.3.3:
NUMA Multiprocessors / 8.3.4:
COMA Multiprocessors / 8.3.5:
Message-Passing Multicomputers / 8.4:
Interconnection Networks / 8.4.1:
MPPs-Massively Parallel Processors / 8.4.2:
Cluster Computing / 8.4.3:
Communication Software for Multicomputers / 8.4.4:
Scheduling / 8.4.5:
Application-Level Shared Memory / 8.4.6:
Performance / 8.4.7:
Grid Computing / 8.5:
Suggestions for Further Reading / 8.6:
Introduction and General Works / 9.1.1:
Binary and Floating-Point Numbers / 9.1.2:
Assembly Language Programming / 9.1.10:
Alphabetical Bibliography / 9.2:
Finte-Precision Numbers / A:
Radix Number Systems / A.2:
Conversion From One Radix to Another / A.3:
Negative Binary Numbers / A.4:
Binary Arithmetic / A.5:
Principles of Floating Point / B:
IEEE Floating-Point Standard 754 / B.2:
Overview / C:
Assembly Language / C.1.1:
A Small Assembly Language Program / C.1.2:
The 8088 Processor / C.2:
The Processor Cycle / C.2.1:
The General Registers / C.2.2:
Pointer Registers / C.2.3:
Memory and Addressing / C.3:
Memory Organization and Segments / C.3.1:
The 8088 Instruction Set / C.3.2:
Move, Copy and Arithmetic / C.4.1:
Logical, Bit and Shift Operations / C.4.2:
Loop and Repetitive String Operations / C.4.3:
Jump and Call Instructions / C.4.4:
Subroutine Calls / C.4.5:
System Calls and System Subroutines / C.4.6:
Final Remarks on the Instruction Set / C.4.7:
The Assembler / C.5:
The ACK-Based Tutorial Assembler as88 / C.5.1:
Some Differences with Other 8088 Assemblers / C.5.3:
The Tracer / C.6:
Tracer Commands / C.6.1:
Getting Started / C.7:
Examples / C.8:
Hello World Example / C.8.1:
General Registers Example / C.8.2:
Call Command and Pointer Registers / C.8.3:
Debugging an Array Print Program / C.8.4:
Introduction / 1:
Computer Systems Organization / 2:
The Digital Logic Level / 3:
7.

図書

図書
タンネンバウム [著] ; 齊藤忠夫, 小野欽司, 発田弘監訳
出版情報: 東京 : 丸善, 1992.7  xiii,760p ; 22cm
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8.

図書

図書
A. S. タネンバウム著 ; 引地信之, 引地美恵子訳
出版情報: 東京 : トッパン, 1995.11  xx, 828p ; 24cm
所蔵情報: loading…
9.

図書

図書
Andrew S. Tanenbaum
出版情報: Englewood Cliffs, N.J. : Prentice-Hall, c1981  xv, 517 p. ; 24 cm
所蔵情報: loading…
10.

図書

図書
Andrew S. Tanenbaum
出版情報: Upper Saddle River, N.J. : Prentice Hall PTR, 1996  xvii, 813 p. ; 25 cm
所蔵情報: loading…
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