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1.

図書
図書
1. Handbook of III-V heterojunction bipolar transistors (: cloth : alk. paper)
William Liu
出版情報: New York : Wiley, c1998  xiv, 1284 p. ; 26 cm
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目次情報: 続きを見る
Basic Properties and Device Physics of III-V Materials
Two-Terminal Heterojunction Devices
D.C
Current Gain
Nonideal D.C
Characteristics
Thermal-Electrical Properties
Collapse of Current Gain
Failure Mechanisms and Reliability Issues
Small-Signal Properties
Epitaxial Layer Design
Geometrical Layout Design
Power Amplifier
Distortion and Noise
Switching Characteristics and Spice Models
Transistor Fabrication
Measured Transistor Performances
Appendices
Glossary of Symbols
Index
Basic Properties and Device Physics of III-V Materials
Two-Terminal Heterojunction Devices
D.C
2.

図書
図書
2. Analysis and design of analog integrated circuits. 2nd ed
Paul R. Gray, Robert G. Meyer
出版情報: New York : Wiley, c1984  xvii, 771 p. ; 25 cm
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Models for Integrated-Circuit Active Devices / Chapter 1：
Introduction / 1.1：
Depletion Region of a pn Junction / 1.2：
Large-Signal Behavior of Bipolar Transistors / 1.3：
Small-Signal Models of Bipolar Transistors / 1.4：
Large Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors / 1.5：
Small-Signal Models of the MOS Transistors / 1.6：
Short-Channel Effects in MOS Transistors / 1.7：
Weak Inversion in MOS Transistors / 1.8：
Substrate Current Flow in MOS Transistors / 1.9：
Summary of Active-Device Parameters / A.1.1：
Bipolar, MOS, and BiCMOS Integrated-Circuit Technology / Chapter 2：
Basic Processes in Integrated-Circuit Fabrication / 2.1：
High-Voltage Bipolar Integrated-Circuit Fabrication / 2.3：
Advanced Bipolar Integrated-Circuit Fabrication / 2.4：
Active Devices in Bipolar Analog Integrated Circuits / 2.5：
Passive Components in Bipolar Integrated Circuits / 2.6：
Modifications to the Basic Bipolar Process / 2.7：
MOS Integrated-Circuit Fabrication / 2.8：
Active Devices in MOS Integrated Circuits / 2.9：
Passive Components in MOS Technology / 2.10：
BiCMOS Technology / 2.11：
Heterojunction Bipolar Transistors / 2.12：
Interconnect Delay / 2.13：
Economics of Integrated-Circuit Fabrication / 2.14：
Packaging Considerations for Integrated Circuits / 2.15：
SPICE Model-Parameter Files / A.2.1：
Single-Transistor and Multiple-Transistor Amplifiers / Chapter 3：
Device Model Selection for Approximate Analysis of Analog Circuits / 3.1：
Two-Port Modeling of Amplifiers / 3.2：
Basic Single-Transistor Amplifier Stages / 3.3：
Multiple-Transistor Amplifier Stages / 3.4：
Differential Pairs / 3.5：
Elementary Statistics and the Gaussian Distribution / A.3.1：
Current Mirrors, Active Loads, and References / Chapter 4：
Current Mirrors / 4.1：
Active Loads / 4.3：
Voltage and Current References / 4.4：
Matching Considerations in Current Mirrors / A.4.1：
Input Offset Voltage of Differential Pair with Active Load / A.4.2：
Output Stages / Chapter 5：
The Emitter Follower As an Output Stage / 5.1：
The Source Follower As an Output Stage / 5.3：
Class B Push-Pull Output Stage / 5.4：
CMOS Class AB Output Stages / 5.5：
Operational Amplifiers with Single-Ended Outputs / Chapter 6：
Applications of Operational Amplifiers / 6.1：
Deviations from Ideality in Real Operational Amplifiers / 6.2：
Basic Two-Stage MOS Operational Amplifiers / 6.3：
Two-Stage MOS Operational Amplifiers with Cascodes / 6.4：
MOS Telescopic-Cascode Operational Amplifiers / 6.5：
MOS Folded-Cascode Operational Amplifiers / 6.6：
MOS Active-Cascode Operational Amplifiers / 6.7：
Bipolar Operational Amplifiers / 6.8：
Design Considerations for Bipolar Monolithic Operational Amplifiers / 6.9：
Frequency Response of Integrated Circuits / Chapter 7：
Single-Stage Amplifiers / 7.1：
Multistage Amplifier Frequency Response / 7.3：
Analysis of the Frequency Response of the 741 Op Amp / 7.4：
Relation Between Frequency Response and Time Response / 7.5：
Feedback / Chapter 8：
Ideal Feedback Equation / 8.1：
Gain Sensitivity / 8.2：
Effect of Negative Feedback on Distortion / 8.3：
Feedback Configurations / 8.4：
Practical Configurations and the Effect of Loading / 8.5：
Single-Stage Feedback / 8.6：
The Voltage Regulator as a Feedback Circuit / 8.7：
Feedback Circuit Analysis Using Return Ratio / 8.8：
Modeling Input and Output Ports in Feedback Circuits / 8.9：
Frequency Response and Stability of Feedback Amplifiers / Chapter 9：
Relation Between Gain and Bandwidth in Feedback Amplifiers / 9.1：
Instability and the Nyquist Criterion / 9.3：
Compensation / 9.4：
Root-Locus Techniques / 9.5：
Slew Rate / 9.6：
Analysis in Terms of Return-Ratio Parameters / A.9.1：
Roots of a Quadratic Equation / A.9.2：
Nonlinear Analog Circuits / Chapter 10：
Precision Rectification / 10.1：
Analog Multipliers Employing the Bipolar Transistor / 10.3：
Phase-Locked Loops (PLL) / 10.4：
Nonlinear Function Symbols / 10.5：
Noise in Integrated Circuits / Chapter 11：
Sources of Noise / 11.1：
Noise Models of Integrated-Circuit Components / 11.3：
Circuit Noise Calculations / 11.4：
Equivalent Input Noise Generators / 11.5：
Effect of Feedback on Noise Performance / 11.6：
Noise Performance of Other Transistor Configurations / 11.7：
Noise in Operational Amplifiers / 11.8：
Noise Bandwidth / 11.9：
Noise Figure and Noise Temperature / 11.10：
Fully Differential Operational Amplifiers / Chapter 12：
Properties of Fully Differential Amplifiers / 12.1：
Small-Signal Models for Balanced Differential Amplifiers / 12.3：
Common-Mode Feedback / 12.4：
CMFB Circuits / 12.5：
Fully Differential Op Amps / 12.6：
Unbalanced Fully Differential Circuits / 12.7：
Bandwidth of the CMFB Loop / 12.8：
Index
Models for Integrated-Circuit Active Devices / Chapter 1：
Introduction / 1.1：
Depletion Region of a pn Junction / 1.2：
3.

図書
図書
3. The bipolar junction transistor. 2nd ed (: pbk.)
Gerold W. Neudeck
出版情報: Reading, Mass. : Addison-Wesley, c1989  ix, 117 p. ; 24 cm
シリーズ名: Modular series on solid state devices ; v. 3
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Introduction to Bipolar Junction Transistors / 1：
The Ideal Junction Transistor / 2：
Derivations from the Ideal Junction Transistor / 3：
Small Signal Models / 4：
Switching Transients / 5：
Introduction to Bipolar Junction Transistors / 1：
The Ideal Junction Transistor / 2：
Derivations from the Ideal Junction Transistor / 3：
4.

図書
図書
4. Digital bipolar integrated circuits (est.)
Mohamed I. Elmasry
出版情報: New York : Wiley, c1983  xiv, 322 p. ; 24 cm
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5.

図書
図書
5. Silicon-germanium heterojunction bipolar transistors
John D. Cressler, Guofu Niu
出版情報: Boston, MA : Artech House, 2003  xviii, 570 p. ; 24 cm
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6.

図書
図書
6. Fundamentals of modern VLSI devices (: hbk ; : pbk)
Yuan Taur, Tak H. Ning
出版情報: Cambridge, UK ; New York : Cambridge University Press, 1998  xxii, 469 p. ; 26 cm
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Introduction / 1：
Basic device physics / 2：
MOSFET devices / 3：
CMOS device design / 4：
CMOS performance factors / 5：
Bipolar devices / 6：
Bipolar device design / 7：
Bipolar performance factors / 8：
Appendices
Introduction / 1：
Basic device physics / 2：
MOSFET devices / 3：
7.

図書
図書
7. Fundamentals of modern VLSI devices. 2nd ed (: hbk)
Yuan Taur, Tak H. Ning
出版情報: Cambridge, UK ; New York : Cambridge University Press, 2009  xxiii, 656 p. ; 26 cm
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Preface to the first edition
Preface to the second edition
Physical constants and unit conversions
List of symbols
Introduction / 1：
Evolution of VLSI Device Technology / 1.1：
Historical Perspective / 1.1.1：
Recent Developments / 1.1.2：
Modern VLSI Devices / 1.2：
Modern CMOS Transistors / 1.2.1：
Modern Bipolar Transistors / 1.2.2：
Scope and Brief Description of the Book / 1.3：
Basic Device Physics / 2：
Electrons and Holes in Silicon / 2.1：
Energy Bands in Silicon / 2.1.1：
n-Type and p-Type Silicon / 2.1.2：
Carrier Transport in Silicon / 2.1.3：
Basic Equations for Device Operation / 2.1.4：
p-n Junctions / 2.2：
Energy-Band Diagrams for a p-n Diode / 2.2.1：
Abrupt Junctions / 2.2.2：
The Diode Equation / 2.2.3：
Current-Voltage Characteristics / 2.2.4：
Time-Dependent and Switching Characteristics / 2.2.5：
Diffusion Capacitance / 2.2.6：
MOS Capacitors / 2.3：
Surface Potential: Accumulation, Depletion, and Inversion / 2.3.1：
Electrostatic Potential and Charge Distribution in Silicon / 2.3.2：
Capacitances in an MOS Structure / 2.3.3：
Polysilicon-Gate Work Function and Depletion Effects / 2.3.4：
MOS under Nonequilibrium and Gated Diodes / 2.3.5：
Charge in Silicon Dioxide and at the Silicon-Oxide Interface / 2.3.6：
Effect of Interface Traps and Oxide Charge on Device Characteristics / 2.3.7：
Metal-Silicon Contacts / 2.4：
Static Characteristics of a Schottky Barrier Diode / 2.4.1：
Current Transport in a Schottky Barrier Diode / 2.4.2：
Current-Voltage Characteristics of a Schottky Barrier Diode / 2.4.3：
Ohmic Contacts / 2.4.4：
High-Field Effects / 2.5：
Impact Ionization and Avalanche Breakdown / 2.5.1：
Band-to-Band Tunneling / 2.5.2：
Tunneling into and through Silicon Dioxide / 2.5.3：
Injection of Hot Carriers from Silicon into Silicon Dioxide / 2.5.4：
High-Field Effects in Gated Diodes / 2.5.5：
Dielectric Breakdown / 2.5.6：
Exercises
Mosfet Devices / 3：
Long-Channel Mosfets / 3.1：
Drain-Current Model / 3.1.1：
Mosfet I-V Characteristics / 3.1.2：
Subthreshold Characteristics / 3.1.3：
Substrate Bias and Temperature Dependence of Threshold Voltage / 3.1.4：
Mosfet Channel Mobility / 3.1.5：
Mosfet Capacitances and Inversion-Layer Capacitance Effect / 3.1.6：
Short-Channel Mosfets / 3.2：
Short-Channel Effect / 3.2.1：
Velocity Saturation and High-Field Transport / 3.2.2：
Channel Length Modulation / 3.2.3：
Source-Drain Series Resistance / 3.2.4：
Mosfet Degradation and Breakdown at High Fields / 3.2.5：
CMOS Device Design / 4：
Mosfet Scaling / 4.1：
Constant-Field Scaling / 4.1.1：
Generalized Scaling / 4.1.2：
Nonscaling Effects / 4.1.3：
Threshold Voltage / 4.2：
Threshold-Voltage Requirement / 4.2.1：
Channel Profile Design / 4.2.2：
Nonuniform Doping / 4.2.3：
Quantum Effect on Threshold Voltage / 4.2.4：
Discrete Dopant Effects on Threshold Voltage / 4.2.5：
Mosfet Channel Length / 4.3：
Various Definitions of Channel Length / 4.3.1：
Extraction of the Effective Channel Length / 4.3.2：
Physical Meaning of Effective Channel Length / 4.3.3：
Extraction of Channel Length by C-V Measurements / 4.3.4：
CMOS Performance Factors / 5：
Basic CMOS Circuit Elements / 5.1：
CMOS Inverters / 5.1.1：
CMOS NAND and NOR Gates / 5.1.2：
Inverter and NAND Layouts / 5.1.3：
Parasitic Elements / 5.2：
Source-Drain Resistance / 5.2.1：
Parasitic Capacitances / 5.2.2：
Gate Resistance / 5.2.3：
Interconnect R and C / 5.2.4：
Sensitivity of CMOS Delay to Device Parameters / 5.3：
Propagation Delay and Delay Equation / 5.3.1：
Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness / 5.3.2：
Sensitivity of Delay to Power-supply Voltage and Threshold Voltage / 5.3.3：
Sensitivity of Delay to Parasitic Resistance and Capacitance / 5.3.4：
Delay of Two-Way NAND and Body Effect / 5.3.5：
Performance Factors of Advanced CMOS Devices / 5.4：
Mosfets in RF Circuits / 5.4.1：
Effect of Transport Parameters on CMOS Performance / 5.4.2：
Low-Temperature CMOS / 5.4.3：
Bipolar Devices / 6：
n-p-n Transistors / 6.1：
Basic Operation of a Bipolar Transistor / 6.1.1：
Modifying the Simple Diode Theory for Describing Bipolar Transistors / 6.1.2：
Ideal Current-Voltage Characteristics / 6.2：
Collector Current / 6.2.1：
Base Current / 6.2.2：
Current Gains / 6.2.3：
Ideal Ic-VCE Characteristics / 6.2.4：
Characteristics of a Typical n-p-n Transistor / 6.3：
Effect of Emitter and Base Series Resistances / 6.3.1：
Effect of Base-Collector Voltage on Collector Current / 6.3.2：
Collector Current Falloff at High Currents / 6.3.3：
Nonideal Base Current at Low Currents / 6.3.4：
Bipolar Device Models for Circuit and Time-Dependent Analyses / 6.4：
Basic de Model / 6.4.1：
Basic ac Model / 6.4.2：
Small-Signal Equivalent-Circuit Model / 6.4.3：
Emitter Diffusion Capacitance / 6.4.4：
Charge-Control Analysis / 6.4.5：
Breakdown Voltages / 6.5：
Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche / 6.5.1：
Saturation Currents in a Transistor / 6.5.2：
Relation Between BV CEO and BV CBO / 6.5.3：
Bipolar Device Design / 7：
Design of the Emitter Region / 7.1：
Diffused or Implanted-and-Diffused Emitter / 7.1.1：
Polysilicon Emitter / 7.1.2：
Design of the Base Region / 7.2：
Relationship between Base Sheet Resistivity and Collector Current Density / 7.2.1：
Intrinsic-Base Dopant Distribution / 7.2.2：
Electric Field in the Quasineutral Intrinsic Base / 7.2.3：
Base Transit Time / 7.2.4：
Design of the Collector Region / 7.3：
Collector Design When There is Negligible Base Widening / 7.3.1：
Collector Design When There is Appreciable Base Widening / 7.3.2：
SiGe-Base Bipolar Transistors / 7.4：
Transistors Having a Simple Linearly Graded Base Bandgap / 7.4.1：
Base Current When Ge Is Present in the Emitter / 7.4.2：
Transistors Having a Trapezoidal Ge Distribution in the Base / 7.4.3：
Transistors Having a Constant Ge Distribution in the Base / 7.4.4：
Effect of Emitter Depth Variation on Device Characteristics / 7.4.5：
Some Optimal Ge Profiles / 7.4.6：
Base-Width Modulation by VBE / 7.4.7：
Reverse-Mode I-V Characteristics / 7.4.8：
Heterojunction Nature of a SiGe-Base Bipolar Transistor / 7.4.9：
Modern Bipolar Transistor Structures / 7.5：
Deep-Trench Isolation / 7.5.1：
Self-Aligned Polysilicon Base Contact / 7.5.2：
Pedestal Collector / 7.5.4：
SiGe-Base / 7.5.5：
Bipolar Performance Factors / 8：
Figures of Merit of a Bipolar Transistor / 8.1：
Cutoff Frequency / 8.1.1：
Maximum Oscillation Frequency / 8.1.2：
Ring Oscillator and Gate Delay / 8.1.3：
Digital Bipolar Circuits / 8.2：
Delay Components of a Logic Gate / 8.2.1：
Device Structure and Layout for Digital Circuits / 8.2.2：
Bipolar Device Optimization for Digital Circuits / 8.3：
Design Points for a Digital Circuit / 8.3.1：
Device Optimization When there is Significant Base Widening / 8.3.2：
Device Optimization When There is Negligible Base Widening / 8.3.3：
Device Optimization for Small Power-Delay Product / 8.3.4：
Bipolar Device Optimization from Some Data Analyses / 8.3.5：
Bipolar Device Scaling for ECL Circuits / 8.4：
Device Scaling Rules / 8.4.1：
Limits in Bipolar Device Scaling for ECL Circuits / 8.4.2：
Bipolar Device Optimization and Scaling for RF and Analog Circuits / 8.5：
The Single-Transistor Amplifier / 8.5.1：
Optimizing the Individual Parameters / 8.5.2：
Technology for RF and Analog Bipolar Devices / 8.5.3：
Limits in Scaling Bipolar Transistors for RF and Analog Applications / 8.5.4：
Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT / 8.6：
Memory Devices / 9：
Static Random-Access Memory / 9.1：
CMOS SRAM Cell / 9.1.1：
Other Bistable MOSFET SRAM Cells / 9.1.2：
Bipolar SRAM Cell / 9.1.3：
Dynamic Random-Access Memory / 9.2：
Basic DRAM Cell and Its Operation / 9.2.1：
Device Design and Scaling Considerations for a DRAM Cell / 9.2.2：
Nonvolatile Memory / 9.3：
Mosfet Nonvolatile Memory Devices / 9.3.1：
Flash Memory Arrays / 9.3.2：
Floating-Gate Nonvolatile Memory Cells / 9.3.3：
Nonvolatile Memory Cells with Charge Stored in Insulator / 9.3.4：
Exercise
Silicon-on-Insulator Devices / 10：
SOI CMOS / 10.1：
Partially Depleted SOI Mosfets / 10.1.1：
Fully Depleted SOI Mosfets / 10.1.2：
Thin-Silicon SOI Bipolar / 10.2：
Fully Depleted Collector Mode / 10.2.1：
Partially Depleted Collector Mode / 10.2.2：
Accumulation Collector Mode / 10.2.3：
Discussion / 10.2.4：
Double-Gate Mosfets / 10.3：
An Analytic Drain Current Model for Symmetric DG Mosfets / 10.3.1：
The Scale Length of Double-Gate Mosfets / 10.3.2：
Fabrication Requirements and Challenges of DG Mosfets / 10.3.3：
Multiple-Gate Mosfets / 10.3.4：
CMOS Process Flow / Appendix 1：
Outline of a Process for Fabricating Modern n-p-n Bipolar Transistors / Appendix 2：
Einstein Relations / Appendix 3：
Spatial Variation of Quasi-Fermi Potentials / Appendix 4：
Generation and Recombination Processes and Space-Charge-Region Current / Appendix 5：
Diffusion Capacitance of a p-n Diode / Appendix 6：
Image-Force-Induced Barrier Lowering / Appendix 7：
Electron-Initiated and Hole-Initiated Avalanche Breakdown / Appendix 8：
An Analytical Solution for the Short-Channel Effect in Subthreshold / Appendix 9：
Generalized Mosfet Scale Length Model / Appendix 10：
Drain Current Model of a Ballistic Mosfet / Appendix 11：
Quantum-Mechanical Solution in Weak Inversion / Appendix 12：
Power Gain of a Two-Port Network / Appendix 13：
Unity-Gain Frequencies of a Mosfet Transistor / Appendix 14：
Determination of Emitter and Base Series Resistances / Appendix 15：
Intrinsic-Base Resistance / Appendix 16：
Energy-Band Diagram of a Si-SiGe n-p Diode / Appendix 17：
ftand fmax of a Bipolar Transistor / Appendix 18：
References
Index
Preface to the first edition
Preface to the second edition
Physical constants and unit conversions
8.

図書
図書
8. Fundamentals of III-V devices : HBTs, MESFETs, and HFETs/HEMTs
William Liu
出版情報: New York : Wiley, c1999  xii, 505p. ; 25 cm
シリーズ名: A Wiley-Interscience publication
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目次情報: 続きを見る
Basic Properties and Device Physics of III-V Materials
Two-Terminal Heterojunction Devices
HBT D.C. Characteristics
HBT High-Frequency Properties
FET D.C. Characteristics
FET High-Frequency Properties
Transistor Fabrication and Device Comparison
Appendices
Index
Basic Properties and Device Physics of III-V Materials
Two-Terminal Heterojunction Devices
HBT D.C. Characteristics
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