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1.

コンピュータファイル

コンピュータファイル
sponsored by IEEE Computer Society TCCA, ACM SIGARCH ; with support from The Georgia Institute of Technology
出版情報: Los Alamitos, CA : IEEE Computer Society, c1999  1 CD-ROM ; 12 cm
シリーズ名: Computer architecture news ; vol. 27, no. 2 May 1999 special issue
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2.

図書

図書
sponsored by IEEE TCCA, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xv, 331 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Chair
Organizing Committee
Steering Committee
Program Committee
Reviewers
Welcoming Remarks
Keynote Address / Burton J. Smith
Processor Pipelines / Session 1:
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2:
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3:
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5:
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6:
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7:
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8:
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
Author Index
Message from the General Chair
Message from the Program Chair
Organizing Committee
3.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 291 p. ; 28 cm
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目次情報: 続きを見る
General Chair's Message
Program Chair's Message
Conference Organization
Reviewers
Plenary Session
Opening Remarks
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1:
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2:
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3:
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4:
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5:
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A:
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B:
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7:
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8:
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
Author Index
General Chair's Message
Program Chair's Message
Conference Organization
4.

図書

図書
Ron Morrison, Flavio Oquendo (eds.)
出版情報: Berlin : Springer, c2005  xii, 262 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 3527
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5.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xviii, 557 p. ; 27 cm.
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6.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture ... [et al.]
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2005  xv, 363 p. ; 28 cm.
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7.

図書

図書
Tom Conte ... [et al.] (eds.)
出版情報: Berlin : Springer, c2005  xiii, 316 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 3793
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8.

図書

図書
edited by Pierre Dissaux ... [et al.]
出版情報: New York : Springer Science, 2005  vi, 207 p. ; 25 cm
シリーズ名: The International Federation for Information Processing ; 176
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9.

図書

図書
Euromicro Symposium on Digital Systems Design ; Euromicro
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xii, 478 p. ; 28 cm
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目次情報: 続きを見る
Message from the Program Chair
Conferences Committees
Keynote Speeches
Eccentric SoC Architectures as the Future Norm / G. Brebner
NoCs: A New Contract between Hardware and Software / A. Jantsch
Towards the Digitally Named World--Challenges for New Social Infrastructures Based on Information Technologies / H. Yasuura
Customizable Embedded Processor Architectures / P. Petrov ; A. Orailoglu
Processor and Memory Architectures
Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems / S. Chung ; H. Kim ; C. Jhon
Unified Dual Data Caches / B. Juurlink
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors / L. Li ; N. Vijaykrishnan ; M. Kandemir ; M. Irwin ; I. Kadayif
Synthesis (HL, LS, PS)
Reversible Logic Synthesis for Minimization of Full-Adder Circuit / H. Babu ; R. Islam ; A. Chowdhury ; S. Chowdhury
Scheduling and Assignment for Real-time Embedded Systems with Resource Contention / L. Pontani ; D. Dupont
Multi Component Digital Circuit Optimization by Solving FSM Equations / N. Yevtushenko ; S. Zharikova ; M. Vetrova
DYNORA: A New Cache Technique / P. Srivatsan ; P. Sudarshan ; P. Bhaskaran
A Quadruple Precision and Dual Double Precision-Floating Point Multiplier / A. Akkas ; M. Schulte
Causality Constraints for Processor Architectures with Sub-Word Parallelism / R. Schaffer ; R. Merker ; F. Catthoor
A Methodology for the Design of AHB Bus Master Wrappers / M. Bertola ; G. Bois
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges / W. Brunnbauer ; T. Wild ; J. Foag ; N. Pazos
An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices / M. Rawski ; H. Selvaraj ; T. Luba
Variations on Truncated Multiplication / J. Stine ; O. Duverne
Exploring Storage Organization in ASIP Synthesis / M. Jain ; M. Balakrishnan ; A. Kumar
RDSP: A RISC DSP Based on Residue Number System / R. Chaves ; L. Sousa
Operating Region Modelling of Deep-Submicron CMOS Buffers Driving Global Scope Inductive Interconnects / G. Cappuccino
A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages / L. Wang
Information-driven Library-Based Circuit Synthesis / L. Jozwiak ; S. Bieganski ; A. Chojnacki
Special Architectures
Low-power Branch Target Buffer for Application-Specific Embedded Processors
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing / P. Holzenspies ; E. Schepers ; W. Bach ; M. Jonker ; B. Sikkes ; G. Smit ; P. Havinga
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator / M. Bera ; G. Danese ; I. De Lotto ; F. Leporati ; A. Spelgatti
A Two-Step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture / T. Lei ; S. Kumar
System-on-a-Chip
A Novel Specification Model for IP-Based Design / S. Klaus ; S. Huss
An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures / G. Kornaros ; T. Orphanoudakis ; N. Zervos
Design and FPGA Implementation of a Video Scalar with On-chip Reduced Memory Utilization / S. Ramachandran ; S. Srinivasan
Estimating the Utilization of Embedded FPGA Co-Processor / Y. Qu ; J. Soininen
A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors / V. Sklyarov ; I. Skliarova ; A. Oliveira ; A. Ferrari
Fast Heuristics for the Edge Coloring of Large Graphs / M. Hilgemeier ; N. Drechsler ; R. Drechsler
Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures / A. Baniasadi
NOAH, A Tool for Augument Reduction, Serial and Parallel Decomposition of Decision Tables / M. Pleban ; H. Niewiadomski ; P. Buciak ; P. Sapiecha
Design Tools and Resusable Libraries for FPGA-Based Digital Circuits / P. Almeida ; M. Almeida
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming / K. Bhasyam ; K. Bazargan
Reconfigurable Randomized K-way Graph Partitioning / F. Kocan
Multiple Voltage and Frequency Scheduling for Power Minimization / B. Radhakrishnan ; M. Venkatesan
A Fast Additive Normalization Method for Exponential Computation / C. Chen ; R. Chen ; M. Sheu
A VLIW Architecture for Logarithmic Arithmetic / M. Arnold
System-on-a-Chip (2) and Validation/Verification
Testable Design Verification Using Petri Nets / R. Ruzicka
Hierarchical Constraint Conscious RT-level Test Generation / O. Sinanoglu
A System-on-Chip Implementation of the IEEE 802.11 a MAC Layer / G. Panic ; D. Dietterle ; Z. Stamenkovic ; K. Tittelbach-Helmrich
The Application of Formal Verification to SPW Designs / B. Akbarpour ; S. Tahar
Applications of (Embedded) Digital Systems
Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm / F. Traugott ; K. Andersson ; A. Lofgren ; L. Lindh
A New Algorithm for High-Speed Projection in Point Rendering Applications / M. Amor ; M. Boo ; A. del Rio ; M. Wand ; W. Strasser
Sensor Platform Design for Automotive Applications / M. De Marinis ; L. Fanucci ; A. Giambastiani ; A. Renieri ; A. Rocchi ; C. Rosadini ; C. Sicilia ; D. Sicilia
Specification and Modeling
Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC / R. Fernandez-Ramos ; J. Romero-Sanchez ; F. Rios-Gomez ; J. Martin-Canales
T&D-Bench+--A Software Environment for Modeling and Simulation of State-of-the-Art Processors / S. Soares ; F. Wagner
Back-Traced Deductive-Parallel Fault Simulation for Digital Systems / V. Hahanov ; R. Ubar ; S. Hyduke
Temperature Influence on Power Consumption and Time Delay / A. Golda ; A. Kos
A Real Time Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications / O. Benderli ; Y. Tekmen ; N. Ismailoglu
Understanding Video Pixel Processing Applications for Flexible Implementations / O. Gangwal ; J. Janssen ; S. Rathnam ; E. Bellers ; M. Duranton
Power/Area Analysis and Optimization of a DS-SS Receiver for an Integrated Sensor Microsystem / N. Aydin ; T. Arslan ; D. Cumming
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits / M. Muroyama ; A. Hyodo ; T. Okuma
Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration / A. Wellig ; J. Zory
Poster Papers
Analytical Bounds on the Threads in IXP 1200 Network Processor / S. Ramakrishna ; H. Jamadagni
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique / G. Papa ; J. Silc
Exact Numerical Processing / J. Chamizo ; J. Pascual ; H. Mora
Stochastic Reconfigurable Hardware for Neural Networks / N. Nedjah ; L. Mourelle
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs / R. Czarnecki ; S. Deniziak ; K. Sapiecha
Distributing SoC Simulations over a Network of Computers / J. Riihimaki ; V. Helminen ; K. Kuusilinna ; T. Hamalainen
FC-Min: A Fast Multi-Output Boolean Minimizer / P. Fiser ; J. Hlavicka ; H. Kubatova
A Methodology for Designing Communication Architectures for Multiprocessor SoCs / V. Dvorak ; V. Kutalek
Compiler-Directed Management of Instruction Accesses / G. Chen ; W. Zhang ; I. Kolcu ; U. Sezer
Test Scheduling for Embedded Systems / Z. Kotasek ; D. Mika ; J. Strnadel
Author Index
Message from the Program Chair
Conferences Committees
Keynote Speeches
10.

図書

図書
Association for Computing Machinery
出版情報: New York : Association for Computing Machinery, c2009  xii, 493 p. ; 28 cm
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