Message from the Symposium Chairs |
Committees |
Yield and Defects / Session 1: |
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs / X. Wang ; M. Ottavi ; F. Lombardi |
Reliability Estimation Model of IC's Interconnect Based on Uniform Distribution of Defects on a Chip / T. Zhao ; X. Duan ; Y. Hao |
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration / M. Lu ; Y. Savaria ; B. Qiu ; J. Taillefer |
Calibration of Open Interconnect Yield Models / D. de Vries ; P. Simon |
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults / T. Feng ; N. Park ; Y. Kim ; V. Piuri |
Optoelectronics / Session 2: |
Level-Hybrid Optoelectronic TESH Interconnection Network / V. Jain ; G. Chapman |
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS) / S. Djaja ; D. Cheung ; Y. Audet |
Fault Analysis, Injection & Simulation / Session 3: |
Clock Calibration Faults and Their Impact on Quality of High Performance Microprocessors / C. Metra ; T. Mak ; D. Rossi |
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs / M. Alderighi ; F. Casini ; S. D'Angelo ; M. Mancini ; A. Marmo ; S. Pastore ; G. Sechi |
CodSim--A Combined Delay Fault Simulator / W. Qiu ; X. Lu ; Z. Li ; D. Walker ; W. Shi |
Test & Diagnosis / Session 4: |
BIST Based Fault Diagnosis Using Ambiguous Test Set / H. Takahashi ; Y. Tsugaoka ; H. Ayano ; Y. Takamatsu |
On the Test and Diagnosis of the Perfect Shuffle / L. Schiano |
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri |
Current Test & Diagnosis / Session 5: |
3DSDM: A 3 Data-Source Diagnostic Method / Y. Hariri ; C. Thibeault |
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits / M. Dragic ; M. Margala |
CROWNE: Current Ratio Outliers with Neighbor Estimator / S. Sabade |
Chip Level Power Supply Partitioning for I[subscript DDQ] Testing Using Built-In Current Sensors / A. Prasad |
Test Generation & Application / Session 6: |
ATE-Amenable Test Data Compression with No Cyclic Scan Registers / H. Hashempour |
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment / F. Zhang ; Y. Lee ; T. Kane ; M. Momenzadeh ; Y.-B. Kim ; F. Meyer ; S. Max ; P. Perkinson |
Function-Based Dynamic Compaction and Its Impact on Test Set Sizes / J. Wingfield ; J. Dworak ; M. Mercer |
Constrained ATPG for Broadside Transition Testing / X. Liu ; M. Hsiao |
Scan Design & Test / Session 7: |
Test Compaction by Using Linear-Matrix Driven Scan Chains / S. Bhatia |
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST / D. Ghosh ; S. Bhunia ; K. Roy |
Design Scan Test Strategy for Single Phase Dynamic Circuits / C.-H. Cheng |
BIST / Session 8: |
Scan-Based BIST Diagnosis Using an Embedded Processor / K. Balakrishnan ; N. Touba |
Hybrid BIST Using an Incrementally Guided LFSR / C. Krishna |
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture / G. Jervan ; P. Eles ; Z. Peng ; R. Ubar ; M. Jenihhin |
Error Correcting Codes / Session 9: |
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems / P. Lala |
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols / H. Kaneko ; E. Fujiwara |
Quadruple Time Redundancy Adders / W. Townsend ; J. Abraham ; E. Swartzlander, Jr. |
Error Correcting Codes for Crosstalk Effect Minimization / S. Cavallotti |
Invited Talk |
A View from the Bottom: Nanometer Technology AC Parametric Failures--Why, Where, and How to Detect / C. Hawkins ; A. Keshavarzi ; J. Segura |
Analogue & Mixed Signal Test / Session 10: |
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation / Y. Miura ; D. Kato |
An Approach for Selection of Test Points for Analog Fault Diagnosis / K. Pinjala ; B. Kim |
BiST Model for IC RF-Transceiver Front-End / J. Dabrowski |
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits / J. Emmert ; J. Cheatham ; B. Jagannathan ; S. Umarani |
Defect Tolerance and Testing / Session 11: |
Thermal Management of High Performance Microprocessors in Burn-In Environment / A. Vassighi ; O. Semenov ; M. Sachdev |
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems / Y. Zhang ; K. Chakrabarty |
Fault Tolerant Multi-layer Neural Networks with GA Training / E. Sugawara ; M. Fukushi ; S. Horiguchi |
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels / A. Ammari ; R. Leveugle ; M. Sonza-Reorda ; M. Violante |
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs / K. Rokas ; Y. Makris ; D. Gizopoulos |
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture / S. Sharifi ; M. Hosseinabadi ; P. Riahi ; Z. Navabi |
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals |
Fault Tolerant Hopfield Associative Memory on Torus / R. Ayoubi ; H. Ziade ; M. Bayoumi |
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study / B. Nicolescu ; P. Peronnard ; R. Velazco |
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip / A. Larsson ; E. Larsson |
Regressive Testing for System-on-Chip with Unknown-Good-Yield / N.-J. Park ; B. Jin ; K. George ; M. Choi |
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker / G. Cardarilli ; S. Pontarelli ; M. Re ; A. Salsano |
Application-Dependent Testing of FPGA Interconnects / M. Tahoori |
Automatic Modification of Sequential Circuits for Self-Checking Implementation / S. Di Francescantonio ; M. Omana |
Control Constrained Resource Partitioning for Complex SoCs / D. Zhao ; S. Upadhyaya |
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits / K. Mohanram |
FPGA & Memory Test / Session 12: |
An Integrated Design Approach for Self-Checking FPGAs / C. Bolchini ; F. Salice ; D. Sciuto ; R. Zavaglia |
Power-Constrained Embedded Memory BIST Architecture / B. Fang ; N. Nicolici |
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities / M. Nicolaidis ; N. Achouri ; L. Anghel |
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator / R. Aitken ; N. Dogra ; D. Gandhi ; S. Becker |
An Efficient Functional Test for the Massively-Parallel C-RAM Logic-Enhanced Memory Architecture / X. Sun ; B. Cockburn ; D. Elliott |
Design Verification & Synthesis / Session 13: |
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models / H. Zarandi ; S. Miremadi ; A. Ejlali |
Preliminary Validation of an Approach Dealing with Processor Obsolescence / S. Saleh ; S. Deswaertes ; A. El Moucary |
SoC & Core Test / Session 14: |
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core / G. Zeng ; H. Ito |
A Unified SoC Test Approach Based on Test Data Compression and TAM Design / V. Iyengar ; A. Chandra |
Embedded Compact Deterministic Test for IP-Protected Cores / A. Kinsman ; J. Hewitt |
System Reliability / Session 15: |
System-Level Analysis of Fault Effects in Automotive Environment / F. Corno ; S. Tosato ; P. Gabrielli |
Dependability Analysis of CAN Networks: An Emulation-Based Approach / J. Perez ; M. Sonza Reorda |
Fault Tolerance / Session 16: |
Exploiting Instruction Redundancy for Transient Fault Tolerance / T. Sato |
An Integrated Fault-Tolerant Design Framework for VLIW Processors / Y.-Y. Chen ; S.-J. Horng ; H.-C. Lai |
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code / S. Almukhaizim |
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead / V. Kumar ; J. Lach |
Soft Errors / Session 17: |
Soft-Error Detection Using Control Flow Assertions / O. Goloubeva ; M. Rebaudengo |
SIED: Software Implemented Error Detection |
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits / A. Maheshwari ; W. Burleson |
Author Index |
Message from the Symposium Chairs |
Committees |
Yield and Defects / Session 1: |