| Foreword |
| Organizing Committee |
| Program Committee |
| Reviewers |
| Tutorials |
| Keynote Speech |
| Invited Talk |
| TTTC Introduction |
| Call for Papers of ATS'05 |
| TTEP Introduction |
| SOC Testing / Session A1： |
| Multi-frequency Test Access Mechanism Design for Modular SOC Testing / Q. Xu ; N. Nicolici |
| Rapid and Energy-Efficient Testing for Embedded Cores / Y. Han ; Y. Hu ; H. Li ; X. Li ; A. Chandra |
| Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy / J. Xing ; H. Wang ; S. Yang |
| Adding Testability to an Asynchronous Interconnect for GALS SoC / A. Efthymiou ; J. Bainbridge ; D. Edwards |
| Low-Power Testing / Session B1： |
| Test Power Reduction with Multiple Capture Orders / K.-J. Lee ; S.-J. Hsu ; C.-M. Ho |
| Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths / Z. You ; K. Yamaguchi ; M. Inoue ; J. Savir ; H. Fujiwara |
| Low Power BIST with Smoother and Scan-Chain Reorder / N.-C. Lai ; Y.-H. Fu ; S.-J. Wang |
| Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction / Y. Higami ; S. Kajihara ; S. Kobayashi ; Y. Takamatsu |
| Analog BIST / Session C1： |
| A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters / H.-W. Ting ; B.-D. Liu ; S.-J. Chang |
| A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC / G.-X. Chen ; C.-L. Lee ; J.-E. Chen |
| A [Sigma - Delta] Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose / H.-C. Hong ; C.-W. Wu ; K.-T. Cheng |
| A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits / S. Bhattacharya ; A. Chatterjee |
| Advanced DFT / Session A2： |
| Multiple Scan Tree Design with Test Vector Modification / K. Miyase ; S. Reddy |
| An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains / J.-C. Rau ; C.-H. Lin ; J.-Y. Chang |
| Scan-Based BIST Using an Improved Scan Forest Architecture / D. Xiang ; M.-J. Chen ; K.-W. Li ; Y.-L. Wu |
| The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time / I.-S. Lee ; T. Ambler ; Y.M. Hur |
| Fault Analysis / Session B2： |
| Testing for Missing-Gate Faults in Reversible Circuits / J.P. Hayes ; I. Polian ; B. Becker |
| Properties of Maximally Dominating Faults / I. Pomeranz |
| I[subscript DDQ] Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment / M. Hashizume ; D. Yoneda ; H. Yotsuyanagi ; T. Tada ; T. Koyama ; I. Morita ; T. Tamesada |
| High Level Fault Injection for Attack Simulation in Smart Cards / K. Rothbart ; U. Neffe ; C. Steger ; R. Weiss ; E. Rieger ; A. Muhlberger |
| Cross-Talk Testing / Session C2： |
| Efficient Identification of Crosstalk Induced Slowdown Targets / S. Nazarian ; S. Gupta ; M. Breuer |
| Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets / W. Sirisaengtaksin |
| A New Path Delay Test Scheme Based on Path Delay Inertia / C.-L. Chen ; M.-S. Wu |
| A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI / K. S.-M. Li ; C.-C. Su |
| Functional Testing / Session A3： |
| Efficient Template Generation for Instruction-Based Self-Test of Processor Cores / K. Kambe |
| Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores / S. Shamshiri ; H. Esmaeilzadeh ; Z. Navabi |
| A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA / C.-L. Chuang ; D.-J. Lu ; C.-N. Liu |
| A Systematic Way of Functional Testing for VLSI Chips / S. Xu |
| Logic BIST / Session B3： |
| Weighted Pseudo-Random BIST for N-detection of Single Stuck-at Faults / C. Yu |
| A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool / S. Biswas ; S. Mukhopadhyay ; A. Patra |
| Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters / M. Arai ; H. Kurokawa ; K. Ichino ; S. Fukumoto ; K. Iwasaki |
| Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults / S. Das ; A. Kundu ; B. Sikdar |
| Fault Diagnosis / Session C3： |
| Compactor Independent Direct Diagnosis / W.-T. Cheng ; K.-H. Tsai ; Y. Huang ; N. Tamarapalli ; J. Rajski |
| Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits / S. Ghosh ; K.-W. Lai ; W.-B. Jone ; S.-C. Chang |
| Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set / H. Takahashi ; Y. Yamamoto |
| Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests / Y. Sato |
| SOC Test Scheduling / Session A4： |
| Hybrid BIST Test Scheduling Based on Defect Probabilities / Z. He ; G. Jervan ; Z. Peng ; P. Eles |
| Pair Balance-Based Test Scheduling for SOCs / Y.-H. Han ; H.-W. Li ; T. Lv ; X.-W. Li |
| RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test / J. Im ; S. Chun ; G. Kim ; J. An ; S. Kang |
| March Based Memory Core Test Scheduling for SOC / W.-L. Wang |
| An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint / S. Edbom ; E. Larsson |
| Memory Testing / Session B4： |
| On Test and Diagnostics of Flash Memories / C.-T. Huang ; J.-C. Yeh ; Y.-Y. Shih ; R.-F. Huang |
| Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution / L. Dilillo ; P. Girard ; S. Pravossoudovitch ; A. Virazel ; S. Borri ; M. Hage-Hassan |
| A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier / Y.-M. Sheng ; M.-J. Hsiao ; T.-Y. Chang |
| An Efficient Diagnosis Scheme for Random Access Memories / J.-F. Li ; C.-D. Huang |
| Evaluation of Intra-Word Faults in Word-Oriented RAMs / S. Hamdioui ; J. Reyes ; Z. Al-Ars |
| Analog Testing / Session C4： |
| Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel / J. Rivoir |
| A Low-Cost Diagnosis Methodology for Pipelined A/D Converters / C.-H. Huang |
| Reconfiguration for Enhanced ALternate Test (REAL Test) of Analog Circuits / G. Srinivasan ; S. Goyal |
| Dynamic Analog Testing via ATE Digital Test Channels / C.-S. Chang ; H.-W. Huang ; D.-S. Tu ; J.C.-H. Lin |
| Testable Design / Session A5： |
| Design and Implementation of Self-Testable Full Range Window Comparator / M. Wong ; Y. Zhang |
| Efficient Test Methodologies for Conditional Sum Adders / C.-C. Hsu |
| A Novel Approach for On-line Testable Reversible Logic Circuit Design / D.-P. Vasudevan ; P. Lala ; J. Parkerson |
| Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores / P. Chaudhuri |
| Testability Analysis / Session B5： |
| Circuit-Width Based Heuristic for Boolean Reasoning / G. Li |
| Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity / D. Das ; T. Inoue ; S. Chakraborty |
| Classification of Sequential Circuits Based on [tau]k Notation / C. Ooi |
| A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits / E. Edirisuriya |
| Yield and Reliability / Session C5： |
| Burn-In Stress Test of Analog CMOS ICs / C.-L. Wey ; M.-Y. Liu |
| Fail Pattern Identification for Memory Built-In Self-Repair / C.-L. Su ; S.-T. Lin ; K.-L. Luo ; Y.-J. Chang |
| Reduce Yield Loss in Delay Defect Detection in Slack Interval / H. Yan ; A. Singh |
| Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing / C.-Y. Huang ; C.-T. Lin ; C.-C. Sue |
| Fault Tolerance / Session A6： |
| Intelligible Test Techniques to Support Error-Tolerance |
| Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment / J.-M. Yang ; D.-F. Zhang |
| Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion / J.-Y. Yeh |
| On Improvement in Fault Tolerance of Hopfield Neural Networks / N. Kamiura ; T. Isokawa ; N. Matsui |
| FPGA Testing and Test Reduction / Session B6： |
| Testing and Diagnosis Techniques for LUT-Based FPGA's / S.-K. Lu ; H.-C. Wu ; S.-J. Yan ; Y.-C. Tsai |
| Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study / D. Han |
| A Test Decompression Scheme for Variable-Length Coding / H. Ichihara ; M. Ochi ; M. Shintani |
| Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test / Y. Shi ; S. Kimura ; N. Togawa ; M. Yanagisawa ; T. Ohtsuki |
| Delay Testing / Session C6： |
| Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-chip Interconnects / L. Wang |
| A Postprocessing Procedure of Test Enrichment for Path Delay Faults |
| Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing / H.-F. Ko |
| Analysis and Attenuation Proposal in Ground Bounce / A. Zenteno ; V. Champac ; M. Renovell ; F. Azais |
| Author Index |
図書
