| Foreword |
| Organizing Committee |
| Steering Committee |
| Program Committee |
| Reviewers |
| VTS '99 Best Paper Award |
| VTS '99 Best Panel Award |
| Test Technology Technical Council |
| Test Technology Education Program: Overview of Tutorials |
| Plenary Session |
| Welcome Message / Adit Singh |
| "Optical Internet: Industry Challenges" / Brian McFadden |
| Program Introduction / Joan Figueras ; Program Chair |
| "Wall Street Perspective on System-on-Chip and Test Technology" / Erach D. Desai |
| Microprocessor Test/Validation |
| At-speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC Microprocessor / N. Tendolkar ; R. Molyneaux ; C. Pyron ; R. Raina |
| Validation of PowerPC Custom Memories using Symbolic Simulation / N. Krishnamurthy ; A K. Martin ; M. S. Abadir ; J. A. Abraham |
| On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set / W-C. Lai ; A. Krstic ; K-T Cheng |
| Low Power BIST and Scan |
| Low Power/Energy BIST Scheme for Datapaths / D. Gizopoulos ; N. Kranitis ; A. Paschalis ; M. Psarakis ; Y. Zorian |
| Low Power BIST via Non-linear Hybrid Cellular Automata / F. Corno ; M. Rebaudengo ; M. Sonza Reorda ; G. Squillero ; M. Violante |
| Static Compaction Techniques to Control Scan Vector Power Dissipation / R. Sankaralingam ; R. R. Oruganti ; N. A. Touba |
| Technology Trends and Their Impact on Test |
| Silicon-on-insulator Technology Impacts on SRAM Testing / R. D. Adams ; P. Shephard III |
| Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation / B. Choi ; D. M. H. Walker |
| Self-checking Circuits versus Realistic Faults in Very Deep Submicron / L. Anghel ; M. Nicolaidis ; I. Alzaher-Noufal |
| Scan Related Approaches |
| BSM2: Next Generation Boundary-Scan Master / F. P. Higgins ; R. Srinivasan |
| Virtual Scan Chains: A Means for Reducing Scan Length in Cores / A. Jas ; B. Pouya |
| A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains / J. Ghosh-Dastidar |
| Defect Driven Techniques |
| A Framework to Minimize Test Escape and Yield Loss during I[subscript DDQ] Testing: A Case Study / H. Cheung ; S. K. Gupta |
| Path Selection for Delay Testing of Deep Sub-micron Devices using Statistical Performance Sensitivity Analysis / J-J. Liou ; K-T. Cheng ; D. A. Mukherjee |
| PROBE: A PPSFP Simulator for Resistive Bridging Faults / C. Y. Lee |
| System-on-chip Test Techniques |
| Test Data Compression for System-on-a-Chip Using Golomb Codes / A. Chandra ; K. Chakrabarty |
| Test and Debug of Networking SoCs: A Case Study / A. Bommireddy ; J. Khare ; S. Shaikh ; S-T. Su |
| Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming |
| Analog Test Techniques |
| Test Generation for Accurate Prediction of Analog Specifications / R. Voorakaranam ; A. Chatterjee |
| A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-based Test / J. Roh |
| Test Selection Based on High Level Fault Simulation for Mixed-signal Systems / S. Ozev ; A. Orailoglu |
| BIST: Arithmetic, Memories and ILAs |
| Integrating Logic BIST in VLSI Designs with Embedded Memories / V. Chickermane ; S. Richter ; C. Barnhart |
| Synthesis for Arithmetic Built-in Self-test / A. P. Stroele |
| A General BIST-amenable Method of Test Generation for Iterative Logic Arrays / K. O. Boateng ; H. Takahashi ; Y. Takamatsu |
| Emerging Test Technology Challenges: Discover the Analysis behind the New ITRS Roadmaps |
| RF/Analog Test of Circuits and Systems |
| Temperature and Process Drift Issues |
| Cold Delay Defect Screening / C.-W. Tseng ; E. J. McCluskey ; X. Shao ; D. M. Wu |
| Thermal Testing: Fault Location Strategies / J. Altet ; A. Rubio ; E. Schaub ; S. Dialhaire ; W. Claeys |
| Detection of CMOS Defects under Variable Processing Conditions / A. Germida ; J. Plusquellic |
| Test Compaction and Design Validation |
| SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration / X. Lin ; W-T. Cheng ; I. Pomeranz ; S. M. Reddy |
| Space Compaction of Test Responses for IP Cores using Orthogonal Transmission Functions / M. Seuring |
| ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits / H. Al-Asaad ; J. P. Hayes |
| Analog BIST |
| An Effective Defect-oriented BIST Architecture for High-speed Phase-locked Loops / S. Kim ; M. Soma ; D. Risbud |
| Characterization of a Pseudo-random Testing Technique for Analog and Mixed-signal Built-in-self-test / J. A. Tofte ; C-K. Ong ; J-L. Huang |
| Hardware Resource Minimization for Histogram-based ADC BIST / M. Renovell ; F. Azais ; S. Bernard ; Y. Bertrand |
| Functional Test and Verification Issues |
| Defuse: A Deterministic Functional Self-test Methodology for Processors / L. Chen ; S. Dey |
| Testing, Verification, and Diagnosis in the Presence of Unknowns / A. Jain ; V. Boppana ; R. Mukherjee ; J. Jain ; M. Fujita ; M. Hsiao |
| Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling / K. Radecka ; Z. Zilic |
| Memory Test |
| Functional Memory Faults: A Formal Notation and a Taxonomy / A. J. van de Goor ; Z. Al-Ars |
| Simulation-based Test Algorithm Generation for Random Access Memories / C-F. Wu ; C-T. Huang ; K-L. Cheng ; C-W. Wu |
| Detection of Inter-port Faults in Multi-port Static RAMs / J. Zhao ; S. Irrinki ; M. Puri ; F. Lombardi |
| Open Defect Detection, Diagnosis and Analog BIST |
| Detectability Conditions for Interconnection Open Defects / V. H. Champac ; A. Zenteno |
| A Technique for Logic Fault Diagnosis of Interconnect Open Defects / S. Venkataraman ; S. B. Drummonds |
| Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations / J. V. Calvano ; V. C. Alves ; M. Lubaszewski |
| How Should Fault Coverage be Defined? |
| External and Embedded Resources: How to Optimize Test Resource Partitioning (TRP)? |
| Biomedical ICs: What is Different About Testing Those ICs? |
| Delay Test, Diagnosis and BIST |
| Bounding Circuit Delay by Testing a Very Small Subset of Paths / M. Sharma ; J. H. Patel |
| On Test Set Generation for Efficient Path Delay Fault Diagnosis / R. C. Tekumalla |
| A Low-speed BIST Framework for High-performance Circuit Testing / H. Speek ; H. G. Kerkhoff ; M. Shashaani ; M. Sachdev |
| BIST Issues |
| Hidden Markov and Independence Models with Patterns for Sequential BIST / L. Brehelin ; O. Gascuel ; G. Caraux ; P. Girard ; C. Landrault |
| Reducing Test Application Time for Built-in-self-test Test Pattern Generators / I. Hamzaoglu |
| Linear Independence as Evaluation Criterion for Two-dimensional Test Pattern Generators / G. Mrugalski ; J. Tyszer ; J. Rajski |
| P1450.1: STIL for the Simulation Environment / P. Wohl ; N. Biggs |
| Extraction of Peak-to-peak and RMS Sinusoidal Jitter using an Analytic Signal Method / T. J. Yamaguchi ; M. Ishida ; T. Watanabe ; T. Ohmi |
| Crosstalk Effect Removal for Analog Measurement in Analog Test Bus / C. Su ; Y-T. Chen |
| High Level ATPG and Test Scheduling |
| High-level Observability for Effective High-level ATPG |
| The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints / V. Muresan ; X. Wang ; M. Vladutiu |
| Testability Alternatives Exploration through Functional Testing / F. Ferrandi ; G. Ferrara ; G. Fornara ; F. Fummi ; D. Sciuto |
| IDDQ Test |
| Efficient Diagnosis of Single/Double Bridging Faults with Delta lddq Probabilistic Signatures and Viterbi Algorithm / C. Thibeault |
| Delta lddq for Testing Reliability / T. J. Powell ; J. Pair ; M. St. John ; D. Counce |
| Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs / S. Jandhyala ; H. Balachandran ; M. Sengupta ; A. P. Jayasumana |
| On-line Testing and Fault Tolerance |
| Fault Escapes in Duplex Systems / S. Mitra ; N. R. Saxena |
| Invariance-based On-line Test for RTL Controller-datapath Circuits / Y. Makris ; I. Bayraktaroglu |
| Word Voter: A New Voter Design for Triple Modular Redundant Systems |
| Panel / Special Session 6： |
| SOC Test: Is P1500 All What You Need? |
| Do I Need This Tool for My Chips to Work? |
| High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability |
| Author Index |
図書
