Howard Jay Siegel, editor ; cosponsored by ACM SIGARCH and the IEEE Computer Society, TCCA, TCCC, TCDP, in cooperation with the School of Electrical Engineering, Purdue University
出版情報:
[New York, NY] : Institute of Electrical and Electronics Engineers , Long Beach, CA : Available from IEEE Computer Society, c1980 124 p. ; 28 cm
edited by Hermann Hellwagner ; held in conjunction with and sponsored by the 11th International Parallel Processing Symposium in cooperation with IEEE Computer Society Technical Committee on Parallel Processing, ACM SIGARCH
出版情報:
Los Alamitos, Calif. : IEEE Computer Society Press, c1997 viii, 135 p. ; 28 cm
sponsored by The IEEE Computer Society Technical Committee on Computer Architecture, IFIP WG 10.3 (Concurrent Systems), Association for Computing Machinery SIGARCH
出版情報:
Los Alamitos, Calif. : IEEE Computer Society Press, c1996 xiv, 304 p. ; 28 cm
International Conference on Embedded Networked Sensor Systems ; Association for Computing Machinery ; Association for Computing Machinery. Special Interest Group on Data Communications ; ACM SIGMOBILE ; ACM-Sigmetrics ; ACM Special Interest Group in Operating Systems ; SIGARCH
出版情報:
New York, N.Y. : Association for Computing Machinery, c2003- v. ; 28 cm
International Symposium on Computer Architecture ; SIGARCH ; Institute of Electrical and Electronics Engineers ; IEEE Computer Society. Technical Committee on Computer Architecture
sponsored by the ACM Special Interest Group on Computer Architecture, the IEEE Computer Society Technical Committees on Supercomputing Applications and Computer Architecture ; in cooperation with Lawrence Livermore Laboratory ... [et al.]
出版情報:
Los Alamitos, Calif. : IEEE Computer Society Press, c1991 xxiii, 917 p. ; 29 cm
sponsored by IEEE Computer Society Technical Committee on Supercomputing Applications, IEEE Computer Society Technical Committee on Computer Architecture, ACM SIGARCH
出版情報:
Los Alamitos, Calif. : IEEE Computer Society Press, c1992 xxiv, 848 p. ; 29 cm
sponsored by the Association for Computing Machinery's Special Interest Group on Programming Languages (SIGPLAN), Special Interest Group on Computer Architecture (SIGARCH) and the International Federation for Information Processing
出版情報:
Reading, MA : Addison-Wesley , New York : Association for Computing Machinery, c1989 vi, 395 p. ; 28 cm
[sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics Engineers]
出版情報:
Washington, D.C. : Computer Society Press of the IEEE, c1990 xv, 378 p. ; 28 cm
sponsored by IEEE CS TC on Data Engineering, ACM SIG on Computer Architecture in cooperation with IEEE CS TC on Distributed Processing, INRIA ; editors, Sushil Jajodia, Won Kim, Abraham Silberschatz
出版情報:
Washington, D.C. : IEEE Computer Society Press , Los Angeles, CA : Additional copies may be ordered from IEEE Computer Society, Terminal Annex, c1988 viii, 221 p. ; 28 cm
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics Engineers
出版情報:
Washington, D.C. : Computer Society Press of the IEEE, c1988 xi, 461 p. ; 28 cm
[sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, the Institute of Electrical and Electronics, Engineers]
出版情報:
Washington, D.C. : IEEE Computer Society Press, c1989 xvii, 426 p. ; 28 cm
International Conference on Architectural Support for Programming Languages and Operating Systems ; Association for Computing Machinery ; SIGARCH ; ACM Special Interest Group in Operating Systems ; ACM Special Interest Group in Programming Languages
出版情報:
New York, N.Y. : Association for Computing Machinery, c2000 ix, 271 p. ; 28 cm
edited by A. Boukerche, S. K. Das, and S. Majumdar ; sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Committee on Simulation ; in cooperation with ACM SIGSIM, ACM SIGARCH ; supported by University of North Texas, University of Texas at Arlington
出版情報:
Los Alamitos, Calif. : IEEE Computer Society, c2002 xvi, 521 p. ; 28 cm
Single-Chip Multiprocessors: The Rebirth of Parallel Processing / G. SohiKeynote 1：
Multithreading / Session 1：
Constraint Graph Analysis of Multithreaded Programs / H. Cain ; M. Lipasti ; R. Nair
The Impact of Resource Partitioning on SMT Processors / S. Raasch ; S. Reinhardt
Initial Observations of a Simultaneous Multithreading Pentium 4 Processor / N. Tuck ; D. Tullsen
Instruction-Level Parallelism / Session 2：
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture / D.-Y. Chen ; L. Liu ; C. Fu ; S. Yang ; C. Wu ; R. Ju
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency / A. Aggarwal ; M. Franklin
Y-Branches: When You Come to a Fork in the Road, Take It / N. Wang ; M. Fertig ; S. Patel
Cache Optimizations / Session 3：
Optimizing Program Locality through CMEs and GAs / X. Vera ; J. Abella ; A. Gonzalez ; J. Llosa
Miss Rate Prediction across All Program Inputs / Y. Zhong ; S. Dropsho ; C. Ding
Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures / H. Al-Sukhni ; I. Bratt ; D. Connors
Challenges and New Approaches to Program Analysis / M. LamKeynote 2：
Compiler Techniques and Domain-Specific Optimizations / Session 4：
Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems / B. Franke ; M. O'Boyle
Inter-Procedural Loop Fusion, Array Contraction and Rotation / J. Ng ; D. Kulkarni ; W. Li ; R. Cox ; S. Bobholz
Spill Code Minimization by Spill Code Motion / A. Koseki ; H. Komatsu ; T. Nakatani
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on General-Purpose CPU / M. Breternitz, Jr ; H. Hum ; S. Kumar
Logging, Tracing, Profiling / Session 5：
An Efficient Online Path Profiling Framework for Java Just-in-Time Compilers / T. Yasue ; T. Suganuma
Compressing Extended Program Traces Using Value Predictors / M. Burtscher ; M. Jeeradit
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation / M. Garzaran ; M. Prvulovic ; V. Vinals ; J. Llaberia ; L. Rauchwerger ; J. Torrellas
Multiprocessors / Session 6：
Reactive Multi-Word Synchronization for Multiprocessors / P. Ha ; P. Tsigas
Design Trade-offs in High-Throughput Coherence Controllers / A.-T. Nguyen
Memory Hierarchy Design for a Multiprocessor Look-up Engine / J.-L. Baer ; D. Low ; P. Crowley ; N. Sidhwaney
Biomedical Computing and Visualization / C. JohnsonKeynote 3：
Application Characterization / Session 7：
Characterizing and Predicting Program Behavior and Its Variability / E. Duesterwald ; C. Cascaval ; S. Dwarkadas
Redeeming IPC as a Performance Metric for Multithreaded Programs / K. Lepak
Picking Statistically Valid and Early Simulation Points / E. Perelman ; G. Hamerly ; B. Calder
Register Design Issues / Session 8：
Reducing Datapath Energy through the Isolation of Short-Lived Operands / D. Ponomarev ; G. Kucuk ; O. Ergin ; K. Ghose
Resolving Register Bank Conflicts for a Network Processor / X. Zhuang ; S. Pande
edited by Virginio Cantoni, Concettina Guerra ; sponsored by IEEE Computer Society Technical Committees on Pattern Analysis and Recognition, Parallell Processing and Cmputer Architecture ; in cooperation with ACM SIGARCH
出版情報:
Los Alamitos, CA ; Tokyo : IEEE Computer Society, c2000 xi, 364 p. ; 28 cm
The Optimum Pipeline Depth for a Microprocessor / A. Hartstein ; T. Puzak
The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays / M. Hrishikesh ; N. Jouppi ; K. Farkas ; D. Burger ; S. Keckler ; P. Shivakumar
Increasing Processor Performance by Implementing Deeper Pipelines / E. Sprangle ; D. Carmean
Processor Scheduling / Session 2：
Efficient Dynamic Scheduling through Tag Elimination / D. Ernst ; T. Austin
Slack: Maximizing Performance under Technological Constraints / B. Fields ; R. Bodik ; M. Hill
A Large, Fast Instruction Window for Tolerating Cache Misses / A. Lebeck ; J. Koppanalil ; T. Li ; J. Patwardhan ; E. Rotenberg
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing / H.-S. Kim ; J. Smith
Safety and Reliability / Robert P. ColwellSession 3：
Transient-Fault Recovery Using Simultaneous Multithreading / T. Vijaykumar ; I. Pomeranz ; K. Cheng
Detailed Design and Evaluation of Redundant Multithreading Alternatives / S. Mukherjee ; M. Kontz ; S. Reinhardt
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors / M. Prvulovic ; Z. Zhang ; J. Torrellas
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery / D. Sorin ; M. Martin ; D. Wood
Power Aware Architecture / Session 4：
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines / S. Heo ; K. Barr ; M. Hampton ; K. Asanovic
Drowsy Caches: Simple Techniques for Reducing Leakage Power / K. Flautner ; N. Kim ; S. Martin ; D. Blaauw ; T. Mudge
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors / A. Iyer ; D. Marculescu
Memory Systems / Session 5：
Using a User-Level Memory Thread for Correlation Prefetching / Y. Solihin ; J. Lee
Avoiding Initialization Misses to the Heap / J. Lewis ; B. Black ; M. Lipasti
Going the Distance for TLB Prefetching: An Application-Driven Study / G. Kandiraju ; A. Sivasubramaniam
Dynamic Optimization / Session 6：
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior / Z. Hu ; S. Kaxiras ; M. Martonosi
Implementing Optimizations at Decode Time / I. Kim
Managing Multi-configuration Hardware via Dynamic Working Set Analysis / A. Dhodapkar
Data and Storage Networks / Session 7：
Queue Pair IP: A Hybrid Architecture for System Area Networks / P. Buonadonna ; D. Culler
Experiences with VI Communication for Database Storage / Y. Zhou ; A. Bilas ; S. Jagannathan ; C. Dubnicki ; J. Philbin ; K. Li
Vector Architectures / Session 8：
Speculative Dynamic Vectorization / A. Pajuelo ; A. Gonzalez ; M. Valero
Tarantula: A Vector Extension to the Alpha Architecture / R. Espasa ; F. Ardanaz ; J. Emer ; S. Felix ; J. Gago ; R. Gramunt ; I. Hernandez ; T. Juan ; G. Lowney ; M. Mattina ; A. Seznec
Supporting Deep Speculation / Session 9：
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor / V. Krishnan ; Y. Sazeides
Difficult-Path Branch Prediction Using Subordinate Microthreads / R. Chappell ; F. Tseng ; A. Yoaz ; Y. Patt
A Scalable Instruction Queue Design Using Dependence Chains / S. Raasch ; N. Binkert
sponsored by IEEE Technical Committee on Computer Architecture, IEEE Technical Committee on Parallel Processing ; in cooperation with ACM SIGARCH, IBM, Intel, SGI
出版情報:
Los Alamitos, Calif. : IEEE Computer Society, c2000 xi, 309 p. ; 28 cm
"New Challenges in Microarchitecture and Compiler Design" / Fred Pollack
Register Allocation and Analysis
Register Queues: A New Hardware/Software Approach To Efficient Software Pipelining / M. Smelyanskiy ; G. Tyson ; E. Davidson
Global Register Partitioning / J. Hiser ; S. Carr ; P. Sweany
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization / T. Way ; B. Breech ; L. Pollock
Architectural Design
aSOC: A Scalable, Single-Chip Communications Architecture / J. Liang ; S. Swaminathan ; R. Tessier
Address Partitioning in DSM Clusters with Parallel Coherence Controllers / I. Pragaspathy ; B. Falsafi
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications / B. Childers ; J. Davidson
Optimizations and Opportunities
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization / K. Hazelwood ; T. Conte
Exploring the Limits of Sub-Word Level Parallelism / K. Scott
The Dynamic Trace Memoization Reuse Technique / A. da Costa ; F. Franca ; E. Filho
Exploring Sub-Block Value Reuse for Superscalar Processors / J. Huang ; D. Lilja
"Dynamic Optimization: An Online Opportunity" / Michael Smith
High Performance Memory Techniques
Hiding Relaxed Memory Consistency with Compilers / J. Lee ; D. Padua
Neighborhood Prefetching on Multiprocessors Using Instruction History / D. Koppelman
Characterization of Silent Stores / G. Bell ; K. Lepak ; M. Lipasti
Speculation and Prediction
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors / S-J. Lee ; P-C. Yew
A Unified Compiler Framework for Control and Data Speculation / R. Ju ; K. Nomura ; U. Mahadevan ; L-C. Wu
Applying Data Speculation in Modulo Scheduled Loops / R. Hank
Branch Prediction
Branch Prediction in Multi-Threaded Processors / J. Gummaraju ; M. Franklin
The Effect of Code Reordering on Branch Prediction / A. Ramirez ; J. Larriba-Pey ; M. Valero
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions / K. Skadron ; M. Martonosi ; D. Clark
Dynamic Branch Prediction for a VLIW Processor / J. Hoogerbrugge
"Blue Gene" / Monty Denneau
Parallel Computation
Fine Grained Multithreading with Process Calculi / L. Lopes ; F. Silva ; V. Vasconcelos
Data Relation Vectors: A New Abstraction for Data Optimizations / M. Kandemir ; J. Ramanujam
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation / T. Kisuki ; P. Knijnenburg ; M. O'Boyle
Applications
Faster FFTs via Architecture-Cognizance / K. Gatlin ; L. Carter
Hybrid Parallel Circuit Simulation Approaches / E. Naroska ; R-J. Shang ; F. Lai ; U. Schwiegelshohn
Multithreaded Programming of PC Clusters / M. Schulz
Instruction Scheduling
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors / H. Wu ; J. Jaffar ; R. Yap
Instruction Scheduling for Clustered VLIW DSPs / R. Leupers
Efficient Backtracking Instruction Schedulers / S. Abraham ; W. Meleis ; I. Baev
sponsored by the Association for Computing Machinery/Special Interest Group on Computer Architecture ; supported by the following corporations, Intel, Microsoft, Dolphin
出版情報:
New York : Association for Computing Machinery, c2006 xii, 374 p. ; 28 cm
sponsored by IEEE Computer Society Technical Committee on Parallel Processing ; in cooperation with IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Committee on Distributed Processing, ACM SIGARCH
出版情報:
Los Alamitos, Calif. : IEEE Computer Society, c2004 lvi, 289 p. ; 28 cm.
IQ-Services: Resource-Aware Middleware for Heterogeneous Applications / Z. Cai ; G. Eisenhauer ; C. Poellabauer ; K. Schwan ; M. Wolf
Data Partitioning with a Realistic Performance Model of Networks of Heterogeneous Computers / A. Lastovetsky ; R. Reddy
Multisite Resource Selection and Scheduling Algorithm on Computational Grid / W. Zhang ; B. Fang ; H. He ; H. Zhang ; M. Hu
An Execution-Time Estimation Model for Heterogeneous Clusters / Y. Kishimoto ; S. Ichikawa
A Comparison of Static QoS-Based Scheduling Heuristics for a Meta-Task with Multiple QoS Dimensions in Heterogeneous Computing / K. Golconda ; F. Ozguner ; A. Dogan
Capabilities-Based Query Planning in Mediator Systems / J. Tang ; J. Song ; W. Xiao
A High Performance, Low Complexity Algorithm for Compile-Time Task Scheduling in Heterogeneous Systems / T. Hagras ; J. Janecek
Metainformation and Workflow Management for Solving Complex Problems in Grid Environments / H. Yu ; X. Bai ; G. Wang ; Y. Ji ; D. Marinescu
Evaluation of an Unfair Decider Mechanism for the Self-Tuning dynP Job Scheduler / A. Streit
A Framework for Heterogeneous Middleware Security / S. Foley ; T. Quillinan ; M. O'Connor ; B. Mulcahy ; J. Morrison
Improving Performance of Java Applications Using a Coprocessor / F. Li ; M. Kandemir
Automatic Deployment for Hierarchical Network Enabled Servers / E. Caron ; P. Chouhan ; A. Legrand
Static Mapping of Subtasks in a Heterogeneous Ad Hoc Grid Environment / S. Shivle ; r. Castain ; H. Siegel ; A. Maciejewski ; T. Banka ; K. Chindam ; S. Dussinger ; P. Pichumani ; P. Satyasekaran ; W. Saylor ; D. Sendek ; J. Sousa ; J. Sridharan ; P. Sugavanam ; J. Velazco
Performance Improvement in Web Services Invocation Framework / M. Migliardi ; R. Podesta
Application of Lagrangian Receding Horizon Techniques to Resource Management in Ad Hoc Grid Environments / R. Castain
A Hybrid Heuristic for DAG Scheduling on Heterogeneous Systems / R. Sakellariou ; H. Zhao
Parallel Implementation of Strassen's Matrix Multiplication Algorithm for Heterogeneous Clusters / Y. Ohtaki ; D. Takahashi ; T. Boku ; M. Sato
Latency Tolerance through Parallelization of Time in Scientific Applications / A. Srinivasan ; N. Chandra
Performance and Client Heterogeneity in Service-Based Metacomputing / T. Wrzosek ; D. Kurzyniec ; V. Sunderam
Workshop on Parallel and Distributed Real-Time Systems--WPDRTS / Workshop 2：
Resource Management of Highly Configurable Tasks / J. Hansen ; S. Ghosh ; R. Rajkumar ; J. Lehoczky
Quality-Based Adaptive Resource Management Architecture (QARMA): A CORBA Resource Management Service / D. Fleeman ; M. Gillen ; A. Lenharth ; M. Delaney ; L. Welch ; D. Juedes ; C. Liu
Heuristic Resource Allocation Algorithms for Maximizing Allowable Workload in Dynamic, Distributed Real-Time Systems / F. Drews
Robust Partitioning for Reliable Real-Time Systems / R. Seyer ; C. Siemers ; R. Falsett ; K. Ecker ; H. Richter
Iterative Integer Programming Formuation for Robust Resource Allocation in Dynamic Real-Time Systems / S. Gertphol ; V. Prasanna
Time-sensitive Computation of Aggregate Functions over Distributed Imprecise Data / Q. Han ; M. Nguyen ; S. Irani ; N. Venkatasubramanian
Pfair Scheduling of Periodic Tasks with Allocation Constraints on Multiple Processors / D. Liu ; Y. Lee
Improved Conditions for Bounded Tardiness under EPDF Fair Multiprocessor Scheduling / U. Devi ; J. Anderson
Group Scheduling in Systems Software / M. Frisbie ; D. Niehaus ; V. Subramonian ; C. Gill
Cost Efficient Synthesis of Real-Time Systems upon Heterogeneous Multiprocessor Platforms / S. Baruah
Synthesis of Pipelined Systems for the Contemporaneous Execution of Periodic and Aperiodic Tasks with Hard Real-Time Constraints / P. Palazzari ; L. Baldini ; M. Coli
Design of a Real-Time CORBA Event Service Customised for the CAN Bus / R. Finocchiaro ; S. Lankes ; A. Jabs
Message Routing in Multi-segment FTT Networks: The Isochronous Approach / P. Pedreiras ; L. Almeida
Software Organization to Facilitate Dynamic Processor Scheduling / R. Clark ; E. Jensen ; N. Rouquette
Utility-Function Based Resource Allocation for Adaptable Applications in Dynamic, Distributed Real-Time Systems / A. Bruening ; M. Hoefer
Time-Utility Scheduling and Provably Correct Critical Computer-Based Systems / G. Le Lann
On the Joint Utility Accrual Model / H. Wu ; B. Ravindran
CARUSO--An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Applications / U. Brinkschulte ; T. Ungerer ; J. Becker
Worst Case Execution Time Prediction by Static Program Analysis / C. Ferdinand
On Static WCET Analysis vs. Run-time Monitoring of Execution Time / C. Cavanaugh
Timing Analysis: In Search of Multiple Paradigms / F. Mueller
The Case for Dynamic Real-time Task Timing in Modern Real-Time Systems / S. Brandt
Real-Time Communication for Industrial Embedded Systems Using Switched Ethernet / H. Hoang
Managing Communication in Integrated Modular Architectures / S. Gopalakrishnan
Pulse-modulated Radar Display Processor on a Chip / T. Darwich
Peer-to-Peer Reputations / P. Dewan
A Utility-Based Approach to Scheduling Multimedia Streams in Peer-to-Peer Systems / F. Chen
Increasing Object Availability in Peer-to-Peer Systems / M. Ramanathan
A Parallel Architecture for Secure FPGA Symmetric Encryption / E. Swankoski ; R. Brooks ; V. Narayanan ; M. Irwin
Tuning Reconfigurable Microarchitectures for Power Efficiency / A. Dhodapkar ; J. Smith
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling / S. Sezer ; C. Toal ; E. Garcia ; V. Stewart
A New Approach for On-line Placement on Reconfigurable Devices / A. Ahmadinia ; C. Bobda ; M. Bednara ; J. Teich
Improving Java Performance Using Dynamic Method Migration on FPGAs / E. Lattanzi ; A. Gayasen ; L. Benini ; A. Bogliolo
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration / M. Ullmann ; M. Huebner ; B. Grimm
Models and Reconfiguration Problems for Multi Task Hyperreconfigurable Architectures / S. Lange ; M. Middendorf
Runtime Reconfigurable Interfaces--The RTR-IFB Approach / S. Ihmor ; W. Hardt
System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications / E. El-Araby ; M. Taher ; K. Gaj ; T. El-Ghazawi ; D. Caliga ; N. Alexandridis
Embedded Software Integration for Coarse-grain Reconfigurable Systems / P. Schaumont ; K. Sakiyama ; A. Hodjat ; I. Verbauwhede
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development / V. Kalenteridis ; H. Pournara ; K. Siozios ; K. Tatas ; G. Koytroympezis ; I. Pappas ; S. Nikolaidis ; S. Siskos ; D. Soudris ; A. Thanailakis
Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration / F. Weissel
Forward-looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs / R. Huang ; R. Vemuri
Integrated Modeling and Generation of a Reconfigurable Network-on-Chip / D. Ching
Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis / K. Danne
Hardware Assisted Two Dimensional Ultra Fast Placement / M. Handa
System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement / H. Kalte ; M. Porrmann ; U. Ruckert
Non-Contiguous Linear Placement for Reconfigurable Fabrics / C. Ababei ; K. Bazargan
Impacting Education Using FPGAs / D. Bouldin
Developing Large-Scale Field-Programmable Analog Arrays / T. Hall ; C. Twigg ; P. Hasler ; D. Anderson
Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array / J. Starzyk ; Y. Guo ; Z. Zhu
Designing a Runtime Reconfigurable Processor for General Purpose Applications / A. Niyonkuru ; H. Zeidler
A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2[superscript m]) / N. Saqib ; F. Rodriguez-Henriquez ; A. Diaz-Perez
Adaptive Processor: A Model of Stream Processing / S. Takano
Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array / J. Huang ; M. Tahoori ; F. Lombardi
Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs / M. Gokhale ; P. Graham ; E. Johnson ; N. Rollins ; M. Wirthlin
Dynamically Configurable Security for SRAM FPGA Bitstreams / L. Bossuet ; G. Gogniat ; W. Burleson
RECASTER: Synthesis of Fault-Tolerant Embedded Systems Based on Dynamically Reconfigurable FPGAs / C. da Silva ; A. Tokarnia
Adaptive System Architectures / K. Waldschmidt
Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture / P. Heysters ; G. Rauwerda ; G. Smit
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays--Constraints and Methodology / F. Hannig ; H. Dutta
Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing / Y. Ben-Asher ; D. Citron ; G. Haber
A High-Performance and Energy-efficient Architecture for Floating-point Based LU Decomposition on FPGAs / G. Govindu ; S. Choi ; V. Daga ; S. Gangadharpalli ; V. Sridhar
Analysis of High-performance Floating-point Arithmetic on FPGAs / L. Zhuo
Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications / S. Khawam ; T. Arslanm ; F. Westall
Pipelined Multipliers for Reconfigurable Hardware / M. Myjak ; J. Delgado-Frias
Functional Programming for Reconfigurable Computing / A. Strelzoff
A Dynamically-Reconfigurable Image Recognition Processor / K. Maruo ; M. Ichikawa ; N. Miyamoto ; L. Karnan ; T. Yamaguchi ; K. Kotani ; T. Ohmi
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays / M. Kumar ; B. Jayaram ; R. Manimegalai ; V. Kamakoti
Computer Architecture: Challenges and Opportunities for the Next Decade / Tilak Agerwala
Architecture Evaluations / Session 1：
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams / M. Taylor ; W. Lee ; J. Miller ; D. Wentzlaff ; B. Greenwald ; V. Strumpen ; N. Shnidman ; I. Bratt ; H. Hoffmann ; P. Johnson ; J. Kim ; A. Saraf ; J. Psota ; M. Frank|cS. Amarasinghe ; A. Agarwal
Evaluating the Imagine Stream Architecture / J. Ahn ; W. Dally ; B. Khailany ; U. Kapasi ; A. Das
Field-testing IMPACT EPIC Research Results in Itanium 2 / J. Sias ; S. Ueng ; G. Kent ; I. Steiner ; E. Nystrom ; W. Hwu
Parallelism in Microarchitectures / Session 2A：
Wire Delay is Not a Problem for SMT (In the Near Future) / Z. Chishti ; T. Vijaykumar
The Vector-Thread Architecture / R. Krashinsky ; C. Batten ; S. Gerding ; M. Hampton ; B. Pharris ; J. Casper ; K. Asanovic
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance / R. Kumar ; D. Tullsen ; P. Ranganathan ; N. Jouppi ; K. Farkas
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism / Y. Chou ; B. Fahs ; S. Abraham
Memory Consistency / Session 2B：
Memory Ordering: A Value-Based Approach / H. Cain ; M. Lipasti
Transactional Memory Coherence and Consistency / L. Hammond ; V. Wong ; M. Chen ; B. Hertzberg ; J. Davis ; B. Carlstrom ; M. Prabhu ; H. Wijaya ; C. Kozyrakis ; K. Olukotun
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model / S. Hangal ; D. Vahia ; C. Manovit ; J. Lu ; S. Narayanan
SMTp: An Architecture for Next-generation Scalable Multi-threading / M. Chaudhuri ; M. Heinrich
Panel: Supporting ILP in Tiled Architectures: Wasted Effort, or a Good Idea?
Keynote 2
High Performance Throughput Computing / Marc Tremblay ; Sun Microsystems
Power and Energy / Session 3：
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications / C. Hughes ; S. Adve
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor / J. Oliver ; R. Rao ; P. Sultana ; J. Crandall ; E. Czernikowski ; L. Jones ; D. Franklin ; V. Akella ; F. Chong
Power Awareness through Selective Dynamically Optimized Traces / R. Rosner ; Y. Almog ; M. Moffie ; N. Schwartz ; A. Mendelson
Interconnect and I/O / Session 3B：
X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs / L. Bairavasundaram ; M. Sivathanu ; A. Arpaci-Dusseau ; R. Arpaci-Dusseau
Low-Latency Virtual-Channel Routers for On-Chip Networks / R. Mullins ; A. West ; S. Moore
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism / V. Puente ; J. Gregorio ; F. Vallejo ; R. Beivide
Compression and Debugging / Session 4A：
Adaptive Cache Compression for High-Performance Processors / A. Alameldeen ; D. Wood
iWatcher: Efficient Architectural Support for Software Debugging / P. Zhou ; F. Qin ; W. Liu ; Y. Zhou ; J. Torrellas
Superscalars / Session 4B：
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation / S. Yehia ; O. Temam
Prophet/Critic Hybrid Branch Prediction / A. Falcon ; J. Stark ; A. Ramirez ; K. Lai ; M. Valero
Support for Reliability / Session 5A：
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor / C. Weaver ; J. Emer ; S. Mukherjee ; S. Reinhardt
The Case for Lifetime Reliability-Aware Microprocessors / J. Srinivasan ; P. Bose ; J. Rivers
Exploiting Resonant Behavior to Reduce Inductive Noise / M. Powell
Register File / Session 5B：
Use-Based Register Caching with Decoupled Indexing / J. Butts ; G. Sohi
A Content Aware Integer File Organization / R. Gonzalez ; A. Cristal ; D. Ortega ; A. Veidenbaum
Physical Register Inlining / B. Mestan ; E. Gunadi
Performance Methodologies / Session 6A：
A First-Order Superscalar Processor Model / T. Karkhanis ; J. Smith
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies / L. Eckhout ; R. Bell ; B. Stougie ; K. De Bosschere ; L. John
Microarchitectural Concepts / Session 6B：
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs / B. Iyer ; S. Srinivasan ; B. Jacob
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy / A. Parashar ; S. Gurumurthi ; A. Sivasubramaniam
International Workshop on Agent-Oritented Software Engineering Challenges for Ubiquitous and Perasive Computing ; International Conference on Pervasive Services ; SIGARCH ; Association for Computing Machinery
出版情報:
New York. : Association for Computing Machinery, c2008 35 p. ; 28 cm
International Workshop on Use of P2P, Grid and Agents for the Development of Content Networks ; SIGARCH ; IEEE Computer Society ; University of Arizona ; Association for Computing Machinery
出版情報:
New York : Association for Computing Machinery, c2007 81 p. ; 28 cm
sponsored by IEEE Computer Society Technical Committee on Simulation, IEEE Computer Society Technical Committee on Computer Architecture ; in cooperation with ACM SIGSIM, ACM SIGARCH
出版情報:
Los Alamitos, Calif. : IEEE Computer Society, c2001 xii, 432 p. ; 28 cm
Sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing, ACM SIGARCH, IFIP Working Group 10.3 ; with the support of Technical University of Catalunya (UPC) ... [et al.]
出版情報:
Los Alamitos, Calif. : IEEE Computer Society, c2001 x, 305 p. ; 28 cm
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications / T. Sherwood ; E. Perelman ; B. Calder
Modeling Superscalar Processors via Statistical Simulation / S. Nussbaum ; J. Smith
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces / L. Eeckhout ; K. De Bosschere
Efficient Caches / Session 2：
Filtering Techniques to Improve Trace-Cache Efficiency / R. Rosner ; A. Mendelson ; R. Ronen
Reactive-Associative Caches / B. Batson ; T. Vijaykumar
Adaptive Mode Control: A Static-Power-Efficient Cache Design / H. Zhou ; M. Toburen ; E. Rotenberg ; T. Conte
Specialized Instruction Sets / Session 3：
Implementation and Evaluation of the Complex Streamed Instruction Set / B. Juurlink ; D. Tcheressiz ; S. Vassiliadis ; H. Wijshoff
On the Efficiency of Reductions in [mu]-SIMD Media Extensions / J. Corbal ; R. Espasa ; M. Valero
Prediction and Recovery / Justin RattnerSession 4：
Boolean Formula-Based Branch Prediction for Future Technologies / D. Jimenez ; H. Hanson ; C. Lin
Using Dataflow Based Context for Accurate Value Prediction / R. Thomas ; M. Franklin
Recovery Mechanism for Latency Misprediction / E. Morancho ; J. Maria Llaberia ; A. Olive
Memory Optimization / Session 5：
A Cost Framework for Evaluating Integrated Restructuring Optimizations / B. Chandramouli ; J. Carter ; W. Hsieh ; S. McKee
Compiling for the Impulse Memory Controller / X. Huang ; Z. Wang ; K. McKinley
On the Stability of Temporal Data Reference Profiles / T. Chilimbi
Program Optimization / Session 6：
Code Reordering and Speculation Support for Dynamic Optimization Systems / E. Nystrom ; R. Barnes ; M. Merten ; W-M. Hwu
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors / J. Codina ; J. Sanchez ; A. Gonzalez
Cache-Friendly Implementations of Transitive Closure / M. Penner ; V. Prasanna
Technology Implications / Session 7：
Exploring the Design Space of Future CMPs / J. Huh ; D. Burger ; S. Keckler
Area and System Clock Effects on SMT/CMP Processors / J. Burns ; J-L. Gaudiot
Parallel Machines / Joel EmerSession 8：
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms / F. Warg ; P. Stenstrom
Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications / R. Ferreira ; G. Agrawal ; J. Saltz
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors / M. Garzaran ; M. Prvulovic ; Y. Zhang ; A. Jula ; H. Yu ; L. Rauchwerger ; J. Torrellas
Data Prefetching / Session 9：
Optimizing Software Data Prefetches with Rotating Registers / G. Doshi ; R. Krishnaiyer ; K. Muthukumar
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes / N. Kohout ; S. Choi ; D. Kim ; D. Yeung
Data Flow Analysis for Software Prefetching Linked Data Structures in Java / B. Cahoon
Comparing and Combining Read Miss Clustering and Software Prefetching / V. Pai ; S. Adve
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1：
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2：
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3：
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4：
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5：
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A：
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B：
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7：
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8：
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
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