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1.

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図書
1. Proceedings : 18th IEEE VLSI Test Symposium, 30 April-4 May, 2000, Montréal, Québec, Canada
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society, c2000  xxxix, 478 p. ; 28 cm
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Foreword
Organizing Committee
Steering Committee
Program Committee
Reviewers
VTS '99 Best Paper Award
VTS '99 Best Panel Award
Test Technology Technical Council
Test Technology Education Program: Overview of Tutorials
Plenary Session
Welcome Message / Adit Singh
"Optical Internet: Industry Challenges" / Brian McFadden
Program Introduction / Joan Figueras ; Program Chair
"Wall Street Perspective on System-on-Chip and Test Technology" / Erach D. Desai
Microprocessor Test/Validation
At-speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC Microprocessor / N. Tendolkar ; R. Molyneaux ; C. Pyron ; R. Raina
Validation of PowerPC Custom Memories using Symbolic Simulation / N. Krishnamurthy ; A K. Martin ; M. S. Abadir ; J. A. Abraham
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set / W-C. Lai ; A. Krstic ; K-T Cheng
Low Power BIST and Scan
Low Power/Energy BIST Scheme for Datapaths / D. Gizopoulos ; N. Kranitis ; A. Paschalis ; M. Psarakis ; Y. Zorian
Low Power BIST via Non-linear Hybrid Cellular Automata / F. Corno ; M. Rebaudengo ; M. Sonza Reorda ; G. Squillero ; M. Violante
Static Compaction Techniques to Control Scan Vector Power Dissipation / R. Sankaralingam ; R. R. Oruganti ; N. A. Touba
Technology Trends and Their Impact on Test
Silicon-on-insulator Technology Impacts on SRAM Testing / R. D. Adams ; P. Shephard III
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation / B. Choi ; D. M. H. Walker
Self-checking Circuits versus Realistic Faults in Very Deep Submicron / L. Anghel ; M. Nicolaidis ; I. Alzaher-Noufal
Scan Related Approaches
BSM2: Next Generation Boundary-Scan Master / F. P. Higgins ; R. Srinivasan
Virtual Scan Chains: A Means for Reducing Scan Length in Cores / A. Jas ; B. Pouya
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains / J. Ghosh-Dastidar
Defect Driven Techniques
A Framework to Minimize Test Escape and Yield Loss during I[subscript DDQ] Testing: A Case Study / H. Cheung ; S. K. Gupta
Path Selection for Delay Testing of Deep Sub-micron Devices using Statistical Performance Sensitivity Analysis / J-J. Liou ; K-T. Cheng ; D. A. Mukherjee
PROBE: A PPSFP Simulator for Resistive Bridging Faults / C. Y. Lee
System-on-chip Test Techniques
Test Data Compression for System-on-a-Chip Using Golomb Codes / A. Chandra ; K. Chakrabarty
Test and Debug of Networking SoCs: A Case Study / A. Bommireddy ; J. Khare ; S. Shaikh ; S-T. Su
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
Analog Test Techniques
Test Generation for Accurate Prediction of Analog Specifications / R. Voorakaranam ; A. Chatterjee
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-based Test / J. Roh
Test Selection Based on High Level Fault Simulation for Mixed-signal Systems / S. Ozev ; A. Orailoglu
BIST: Arithmetic, Memories and ILAs
Integrating Logic BIST in VLSI Designs with Embedded Memories / V. Chickermane ; S. Richter ; C. Barnhart
Synthesis for Arithmetic Built-in Self-test / A. P. Stroele
A General BIST-amenable Method of Test Generation for Iterative Logic Arrays / K. O. Boateng ; H. Takahashi ; Y. Takamatsu
Emerging Test Technology Challenges: Discover the Analysis behind the New ITRS Roadmaps
RF/Analog Test of Circuits and Systems
Temperature and Process Drift Issues
Cold Delay Defect Screening / C.-W. Tseng ; E. J. McCluskey ; X. Shao ; D. M. Wu
Thermal Testing: Fault Location Strategies / J. Altet ; A. Rubio ; E. Schaub ; S. Dialhaire ; W. Claeys
Detection of CMOS Defects under Variable Processing Conditions / A. Germida ; J. Plusquellic
Test Compaction and Design Validation
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration / X. Lin ; W-T. Cheng ; I. Pomeranz ; S. M. Reddy
Space Compaction of Test Responses for IP Cores using Orthogonal Transmission Functions / M. Seuring
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits / H. Al-Asaad ; J. P. Hayes
Analog BIST
An Effective Defect-oriented BIST Architecture for High-speed Phase-locked Loops / S. Kim ; M. Soma ; D. Risbud
Characterization of a Pseudo-random Testing Technique for Analog and Mixed-signal Built-in-self-test / J. A. Tofte ; C-K. Ong ; J-L. Huang
Hardware Resource Minimization for Histogram-based ADC BIST / M. Renovell ; F. Azais ; S. Bernard ; Y. Bertrand
Functional Test and Verification Issues
Defuse: A Deterministic Functional Self-test Methodology for Processors / L. Chen ; S. Dey
Testing, Verification, and Diagnosis in the Presence of Unknowns / A. Jain ; V. Boppana ; R. Mukherjee ; J. Jain ; M. Fujita ; M. Hsiao
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling / K. Radecka ; Z. Zilic
Memory Test
Functional Memory Faults: A Formal Notation and a Taxonomy / A. J. van de Goor ; Z. Al-Ars
Simulation-based Test Algorithm Generation for Random Access Memories / C-F. Wu ; C-T. Huang ; K-L. Cheng ; C-W. Wu
Detection of Inter-port Faults in Multi-port Static RAMs / J. Zhao ; S. Irrinki ; M. Puri ; F. Lombardi
Open Defect Detection, Diagnosis and Analog BIST
Detectability Conditions for Interconnection Open Defects / V. H. Champac ; A. Zenteno
A Technique for Logic Fault Diagnosis of Interconnect Open Defects / S. Venkataraman ; S. B. Drummonds
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations / J. V. Calvano ; V. C. Alves ; M. Lubaszewski
How Should Fault Coverage be Defined?
External and Embedded Resources: How to Optimize Test Resource Partitioning (TRP)?
Biomedical ICs: What is Different About Testing Those ICs?
Delay Test, Diagnosis and BIST
Bounding Circuit Delay by Testing a Very Small Subset of Paths / M. Sharma ; J. H. Patel
On Test Set Generation for Efficient Path Delay Fault Diagnosis / R. C. Tekumalla
A Low-speed BIST Framework for High-performance Circuit Testing / H. Speek ; H. G. Kerkhoff ; M. Shashaani ; M. Sachdev
BIST Issues
Hidden Markov and Independence Models with Patterns for Sequential BIST / L. Brehelin ; O. Gascuel ; G. Caraux ; P. Girard ; C. Landrault
Reducing Test Application Time for Built-in-self-test Test Pattern Generators / I. Hamzaoglu
Linear Independence as Evaluation Criterion for Two-dimensional Test Pattern Generators / G. Mrugalski ; J. Tyszer ; J. Rajski
P1450.1: STIL for the Simulation Environment / P. Wohl ; N. Biggs
Extraction of Peak-to-peak and RMS Sinusoidal Jitter using an Analytic Signal Method / T. J. Yamaguchi ; M. Ishida ; T. Watanabe ; T. Ohmi
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus / C. Su ; Y-T. Chen
High Level ATPG and Test Scheduling
High-level Observability for Effective High-level ATPG
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints / V. Muresan ; X. Wang ; M. Vladutiu
Testability Alternatives Exploration through Functional Testing / F. Ferrandi ; G. Ferrara ; G. Fornara ; F. Fummi ; D. Sciuto
IDDQ Test
Efficient Diagnosis of Single/Double Bridging Faults with Delta lddq Probabilistic Signatures and Viterbi Algorithm / C. Thibeault
Delta lddq for Testing Reliability / T. J. Powell ; J. Pair ; M. St. John ; D. Counce
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs / S. Jandhyala ; H. Balachandran ; M. Sengupta ; A. P. Jayasumana
On-line Testing and Fault Tolerance
Fault Escapes in Duplex Systems / S. Mitra ; N. R. Saxena
Invariance-based On-line Test for RTL Controller-datapath Circuits / Y. Makris ; I. Bayraktaroglu
Word Voter: A New Voter Design for Triple Modular Redundant Systems
Panel / Special Session 6：
SOC Test: Is P1500 All What You Need?
Do I Need This Tool for My Chips to Work?
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability
Author Index
Foreword
Organizing Committee
Steering Committee
2.

図書
図書
2. Proceedings, 21st IEEE VLSI Test Symposium (VTS 2003) : 27 April-1 May 2003, Napa Valley, California
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xxvii, 432 p. ; 28 cm
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3.

図書
図書
3. Proceedings, 19th IEEE VLSI Test Symposium : VTS 2001 : April 29-3 May 2001, Marina Del Rey, California USA (: [soft.] ; : case.)
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xxxiii, 417 p. ; 28 cm
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目次情報: 続きを見る
Foreword
Acknowledgements
Organizing Committee
Steering Committee
Program Committee
Reviewers
VTS 2000 Best Paper Award
VTS 2000 Best Tutorial Award
Test Technology Technical Council
Test Technology Education Program: Overview of Tutorials
Plenary Session
Welcome Message
Keynote Address: Staying Ahead of the Test Technology Curve / Roger W. Blethen
Program Introduction / Sreejit Chakravarty ; Andre Ivanov
Invited Presentation: Testing the Limits of System-on-Chip / Ronnie Vasishta
BIST Techniques / Session 1：
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme / A. Jas ; C. Krishna ; N. Touba
Compression Technique for Interactive BIST Application / D. Kay ; S. Mourad
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers / M. Psarakis ; D. Gizopoulos ; A. Paschalis ; N. Kranitis ; Y. Zorian
Diagnosis Methods / Session 2：
Diagnosis of Tunneling Opens / J. Li ; E. McCluskey
On Diagnosing Path Delay Faults in an At-Speed Environment / R. Tekumalla ; S. Venkataraman ; J. Ghosh-Dastidar
On Improving the Accuracy Of Multiple Defect Diagnosis / S.-Y. Huang
Test Data Compression / Session 3：
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression / A. Chandra ; K. Chakrabarty
Design of Parameterizable Error-Propagating Space Compactors for Response Observation / A. Morosov ; M. Gossel ; B. Bhattacharya
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip / A. El-Maleh ; S. al Zahir ; E. Khan
Sythesis and Design for Testability / Session 4：
Testable Sequential Circuit Design: A Partition and Resynthesis Approach / R. Chou ; K. Saluja
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency / M. Nummer ; M. Sachdev
Breaking Correlation to Improve Testability / K. Ockunzzi ; C. Papachristou
Scan Chain Design / Session 5：
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals / D. Xiang ; Y. Xu
Multiple Scan Chain Design for Two-Pattern Testing / I. Polian ; B. Becker
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester / D. Bhavsar
Innovative Measurement Techniques / Session 6：
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals / T. Yamaguchi ; M. Soma ; D. Halter ; R. Raina ; J. Nissen ; M. Ishida
Built-in-Chip Testing of Voltage Overshoots in High-Speed SoCs / A. Attarha ; M. Nourani
Current Measurement for Dynamic Idd Test / X. Sun ; B. Vinnakota
Diagnosis and Verification ATPG / Session 7：
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction / M. Amyeen ; W. Fuchs ; I. Pomeranz ; V. Boppana
Semi-Formal Test Generation for a Block of Industrial DSP / J. Dushina ; M. Benjamin ; D. Geist
Defect Analysis and IDDx Diagnosis / Session 8：
Resistive Opens in a Class of CMOS Latches: Analysis and DFT / A. Zenteno ; V. Champac
A Process and Technology-Tolerant I[subscript DDQ] Method for IC Diagnosis / C. Patel ; J. Plusquellic
Panel / Special Session 1：
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue
Hot Topic Session / Special Session 2：
ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing
SOC Testing / Session 9：
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment / T. Tan ; C. Lee
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment / A. Giani ; S. Sheng ; M. Hsiao ; V. Agrawal
High-Level Crosstalk Defect Simulation for System-on-Chip Interconnects / X. Bai ; S. Dey
Online Testing / Session 10：
Design Diversity for Concurrent Error Detection in Sequential Logic Circuits / S. Mitra
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging / E. Sogomonyan ; A. Singh ; J. Rzeha
Design of Redundant Systems Protected against Common-Mode Failures
Self-Test Techniques / Session 11：
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs / J.-R. Huang ; M. Iyer ; K.-T. Cheng
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses / W.-C. Lai
Electrically Induced Stimuli for MEMS Self-Test / B. Charlot ; S. Mir ; F. Parrain ; B. Courtois
Memory Testing / Session 12：
Flash Memory Disturbances: Modeling and Test / M. Mohammad
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories / K.-L. Cheng ; M.-F. Tsai ; C.-W. Wu
An Efficient Methodology for Generating Optimal and Uniform March Tests / S. Al-Harbi ; S. Gupta
Scalable Fault Simulation, Model Build and ATPG Methods / Session 13：
RT-Level Fault Simulation Based on Symbolic Propagation / O. Sinanoglu ; A. Orailoglu
Efficient Transparency Extraction and Utilization in Hierarchical Test / Y. Makris ; V. Patel
Analysis of Testing Methodologies for Custom Designs in PowerPC[superscript TM] Microprocessor / M. Abadir ; J. Zhu ; L.-C. Wang
Test Stimulus Generation for Analog Testing / Session 14：
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization / Y.-T. Chen ; C. Su
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications / F. Azais ; S. Bernard ; Y. Bertrand ; X. Michel ; M. Renovell
Self-Testable Pipelined ADC with Low Hardware Overhead / E. Peralias ; G. Huertas ; A. Rueda ; J. Huertas
Soft Errors and Tolerance for Soft Errors / Special Session 3：
Embedded Tutorial / Special Session 4：
Yield Optimization and Its Relation to Test
ATPG for Design Errors--Is It Possible? / Special Session 5：
Memory Diagnosis / Session 15：
Defect Oriented Fault Diagnosis for Semiconductor Memories Using Charge Analysis, Theory and Experiments / I. de Paul ; M. Rosales ; B. Alorda ; J. Segura ; C. Hawkins ; J. Soden
Enabling Embedded Memory Diagnosis via Test Response Compression / J. Chen ; J. Rajski ; J. Khare ; O. Kebichi ; W. Maly
Automatic Generation of Diagnostic March Tests / D. Niggemeyer ; E. Rudnick
Minimizing Test Power / Session 16：
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator / P. Girard ; L. Guiller ; C. Landrault ; S. Pravossoudovitch ; H.-J. Wunderlich
Test Scheduling for Minimal Energy Consumption under Power Constraints / T. Schuele ; A. Stroele
Reducing Power Dissipation during Test Using Scan Chain Disable / R. Sankaralingam ; B. Pouya
Estimating and Reducing Infant Mortality / Session 17：
Burn-in Failures and Local Region Yield: An Integrated Yield-Reliability Model / T. Barnett ; V. Nelson
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement / M. Khalil ; C.-L. Wey
MINVDD Testing for Weak CMOS ICs / C.-W. Tseng ; R. Chen ; P. Nigh
Novel ATPG Techniques / Session 18：
SPIRIT: A Highly Robust Combinational Test Generation Algorithm / E. Gizdarski ; H. Fujiwara
On the Use of Fault Dominance in n-Detection Test Generation / S. Reddy
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outs / Y.-S. Chang ; M. Breuer
Test Scheduling, Leakage Estimation and Onchip Delay Measurement / Session 19：
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip / V. Iyengar
Average Leakage Current Estimation of CMOS Logic Circuits / J. de Gyvez ; E. van de Wetering
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links / J.-L. Huang
Fault Modeling and BIST Evaluation / Session 20：
Tools for the Characterization of Bipolar CML Testability / G. Monte ; B. Antaki ; S. Patenaude ; Y. Savaria ; C. Thibeault ; P. Trouborst
Testing of Dynamic Logic Circuits Based on Charge Sharing / K. Heragu ; M. Sharma ; R. Kundu ; R. Blanton
An Evaluation of Pseudo Random Testing for Detecting Real Defects / S. Davidson
Showcase / Special Session 6：
IP and Automation to Support IEEE P1500
Reliability Beyond GHz / Special Session 7：
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? / Special Session 8：
Author Index
Foreword
Acknowledgements
Organizing Committee
4.

図書
図書
4. Proceedings, 20th IEEE VLSI Test Symposium (VTS 2002) : 28 April-2 May 2002, Monterey, California
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xxxvii, 452 p. ; 28 cm
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Foreword
VTS 20th Anniversary Page
Acknowledgements
Organizing Committee
Steering Committee
Program Committee
Reviewers
Test Technology Technical Council
Test Technology Educational Program: Overview of Tutorials
Plenary Session
Welcome Message
Keynote Address
Program Introduction
Plenary Address: Business and Technical Challenges for Testing the Ghz Age
Microprocessor Test / Session 1：
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC Instruction Set Architecture / N. Tendolkar ; R. Raina ; R. Woltenberg ; X. Lin ; B. Swanson ; G. Aldrich
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs / A. Pandey ; J. Patel
Scan Islands--A Scan Partitioning Architecture and Its Implementation on the Alpha 21364 Processor / D. Bhavsar ; R. Davies
Applications of Very Low Voltage and Slow Speed Testing / Session 2：
Very Low Voltage Testing of SOI Integrated Circuits / E. MacDonald ; N. Touba
Performance Comparison of VLV, ULV, and ECR Tests / W. Jiang ; E. Peterson
Experimental Results for Slow-Speed Testing / C.-W. Tseng ; J. Li ; E. McCluskey
Innovations in Test Automation / IP Session 1：
Advancements in Scan-Based Testing / Session 3：
Scan-Path with Directly Duplicated and Inverted Duplicated Registers / M. Goessel ; A. Singh ; E. Sogomonyan
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits / A. El-Maleh ; A. Al-Suwaiyan
Logic BIST and Scan Test Techniques for Multiple Identical Blocks / K. Arabi
Burn-in Reduction or Alternatives / Session 4：
Statistical Post-Processing at Wafersort--An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies / R. Madge ; M. Rehani ; K. Cota ; W. Daasch
Yield-Reliability Modeling: Experimental Verification and Application to Burn-in Reduction / T. Barnett ; M. Grady ; K. Purdy
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-Based I[subscript DDQ] Testing for Burn-in Reduction / S. Sabade ; D. Walker
DFT Testers 1 / IP Session 2：
A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?
Test Set Compression Techniques / Session 5：
How Effective Are Compression Codes for Reducing Test Data Volume? / A. Chandra ; K. Chakrabarty ; R. Medina
Test Vector Compression Using EDA-ATE Synergies / A. Khoche ; E. Volkerink ; J. Rivoir ; S. Mitra
On Test Data Volume Reduction for Multiple Scan Chain Designs / S. Reddy ; K. Miyase ; S. Kajihara ; I. Pomeranz
Analog BIST / Session 6：
Spectrum-Based BIST in Complex SoCs / G. Kasturirangan ; M. Hsiao
A Self Calibrated ADC BIST Methodology / H.-K. Chen ; C.-H. Wang ; C.-C. Su
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus / C.-K. Ong ; K.-T. Cheng
DFT Testers 2 / IP Session 3：
A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?
Increased Efficiency Testing / Session 7：
Testing High-Speed SoCs Using Low-Speed ATEs / M. Nourani ; J. Chin
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs / M. Iyer
On Using Efficient Test Sequences for BIST / R. David ; P. Girard ; C. Landrault ; S. Pravossoudovitch ; A. Virazel
Controlling and Reducing Test Power / Session 8：
Controlling Peak Power during Scan Testing / R. Sankaralingam
Test Vector Modification for Power Reduction during Scan Testing / K. Ishida
Test Power Reduction through Minimization of Scan Chain Transitions / O. Sinanoglu ; I. Bayraktaroglu ; A. Orailoglu
Wireless Test / IP Session 4：
Panel / Special Session 1：
Analog & Mixed Signal BIST: Too Much, Too Little, Too Late?
Test as a Key Enabler for Faster Yield Ramp-Up / Special Session 2：
Diagnosis / Session 9：
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits / M. Amyeen ; W. Fuchs
Diagnosis of Sequence-Dependent Chips
Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation / S.-Y. Huang
Analog Circuit Testing / Session 10：
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus / J. Calvano ; V. Alves ; M. Lubazewski ; A. Mesquita
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division / T. Yamaguchi ; M. Soma ; L. Malarsie ; M. Ishida ; H. Musha
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis / S. Ozev
High Level Test Techniques / Session 11：
Instruction-Based Self-Testing of Processor Cores / N. Kranitis ; D. Gizopoulos ; A. Paschalis ; Y. Zorian
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation / L. Berrojo ; F. Corno ; L. Entrena ; I. Gonzalez ; C. Lopez ; M. Sonza Reorda ; G. Squillero
Program Slicing for Hierarchical Test Generation / V. Vedula ; J. Abraham ; J. Bhadra
SoC Test Infrastructure / Session 12：
Design for Testability and Testing of IEEE 1149.1 Tap Controller / S. Makar
On Using Rectangle Packing for SoC Wrapper/TAM Co-optimization / V. Iyengar ; E. Jan Marinissen
Cluster-Based Test Architecture Design for System-on-Chip / S. Goel
Multi-GigaHertz Testing Challenges and Solutions / IP Session 5：
Test Tools and Algorithms / Session 13：
Exploiting Dominance and Equivalence Using Fault Tuples / K. Dwarakanath ; R. Blanton
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? / N. Krishnamurthy ; M. Abadir
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics / K.-L. Cheng ; J.-C. Yeh ; C.-W. Wang ; C.-T. Huang ; C.-W. Wu
Supply Current Testing / Session 14：
Eigen-Signatures for Regularity-Based I[subscript DDQ] Testing / Y. Okuda
Speeding-up I[subscript DDQ] Measurements / C. Thibeault
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform / S. Bhunia ; K. Roy
IEEE P1500 in Practice / IP Session 6：
Debating the Future of Burn-In / Special Session 3：
Hot Topic / Special Session 4：
Beyond CMOS
Embedded Tutorial / Special Session 5：
Challenges of Mixed-Signal Board Design and Test / G. Roberts
Test Pattern Generation / Session 15：
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits / S. Ohtake ; S. Miwa ; H. Fujiwara
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits / T. Hosokawa ; H. Date ; M. Muraoka
Test Pattern Generation for Signal Integrity Faults on Long Interconnects / A. Attarha
Tester Hardware Modeling and Improvements / Session 16：
Improved Test Monitor Circuit in Power Pin DfT / R. Schuttert ; F. de Jong ; B. Kup
Measuring Stray Capacitance on Tester Hardware / A. Halder ; P. Variyam ; A. Chatterjee ; J. Ridley
Power Supply Transient Signal Analysis under Real Process and Test Hardware Models / J. Plusquellic ; A. Gattiker
FPGA Test Practices / IP Session 7：
Fault Modeling & Extraction / Session 17：
Layout Analysis to Extract open Nets Caused by Systematic Failure Mechanisms / S. Chakravarty ; K. Komeyli ; E. Savage ; M. Carruthers ; B. Stastny ; S. Zachariah
Fault Models for Speed Failures Caused by Bridges and Opens / A. Jain
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits / R. Kundu
Memory Testing / Session 18：
Testing and Diagnosing Embedded Content Addressable Memories / J.-F. Li ; R.-S. Tzeng
Testing Static and Dynamic Faults in Random Access Memories / S. Hamdioui ; Z. Al-Ars ; Ad J. van de Goor
Approximating Infinite Dynamic Behavior for DRAM Cell Defects
IP Session 8
Validation & Test of Network Processors and ASICs
Test-Cost Reduction / Session 19：
Test Economics for Multi-site Test with Modern Cost Reduction Techniques / K. Hilliges
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects / K. Sekar ; S. Dey
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions / P. Gonciari ; B. Al-Hashimi ; N. Nicolici
Oscillation - Based Test / Session 20：
Practical Solutions for the Application of the Oscillation-Based-Test: Start-up and On-Chip Evaluation / D. Vazquez ; G. Huertas ; G. Leger ; A. Rueda ; J. Huertas
Evaluation of the Oscillation-Based Test Methodology for Micro-Electro-Mechanical Systems / V. Beroulle ; Y. Bertrand ; L. Latorre ; P. Nouet
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? / Special Session 6：
Challenges in Nanometric Technology Scaling: Trends and Projections / Special Session 7：
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? / Special Session 8：
Author Index
Foreword
VTS 20th Anniversary Page
Acknowledgements
5.

図書
図書
5. Proceedings : 23rd IEEE VLSI Test Symposium : 1-5 May, 2005, Palm Springs, California
sponsored by IEEE Computer Society Test Technology Technical Council (TTTC)
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xxv, 455 p. ; 28 cm
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6.

図書
図書
6. Proceedings, 22nd IEEE VLSI Test Symposium : 25-29 April 2004, Napa Valley, California
sponsored by IEEE Computer Society Test Technology Technical Council
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  xxvii, 406 p. ; 28 cm
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