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1. Proceedings : the Seventeenth International Symposium on Multiple-Valued Logic, May 26-28, 1987, Boston, Massachusetts, USA (: paper ; : microfiche ; : case)
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Washington, D.C. : IEEE Computer Society Press, c1987  x, 356 p. ; 28 cm
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2. Proceedings : 1999 29th IEEE International Symposium on Multiple-Valued Logic, May 20-22, 1999, Freiburg im Breisgau, Germany (: case ; [: pbk.])
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Albert-Ludwigs-University, Freiburg im Breisgau, Germany
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c1999  xi, 302 p. ; 28 cm
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3.

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3. Proceedings : 30th IEEE International Symposium on Multiple-Valued Logic : (ISMVL) [Portland, Oregon] (: case ; : microfiche)
sponsored by Oregon Center for Advanced Technology Education ...[et al.] ; supported by School of Engineering and Applied Science, Portland State University ...[et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c2000  xiv, 468 p. ; 28 cm
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目次情報: 続きを見る
Message from the Symposium Chair
Message from the Co-Chairs
Reviewers
Invited Address / Session 1：
Computational Neurobiology Meets Semiconductor Engineering / D. Hammerstrom
Neural and Threshold Nets / Session 2a：
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors / J. Shen ; M. Inaba ; K. Tanno ; O. Ishizuka
The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models / M. Matsumoto ; Y. Ueda ; I. Nomoto
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions / M. Syuto
The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons / A. Ngom ; I. Stojmenovic ; R. Tosic
Spectral Methods / Session 2b：
MDD-Based Synthesis of Multi-Valued Logic Networks / R. Drechsler ; M. Thornton ; D. Wessels
Fast Transforms for Multiple-Valued Input Binary Output PLI Logic / B. Falkowski ; S. Rahardja
Computation of Spectral Information from Logic Netlists
Fault Analysis of the Multiple Valued Logic Using Spectral Method / J. Kim ; P. Lala ; Y. Kim ; H. Kim
Neural Networks: Binary Monotonic and Multiple-Valued / J. ZuradaSession 3：
Decomposition and Data Mining / Session 4a：
Data Mining of Weak Functional Decompositions / S. Jaroszewicz ; D. Simovici
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures / A. Chojnacki ; L. Jozwiak
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions / T. Sasao
Algebra I / Session 4b：
Some Properties of Discrete Interval Truth Valued Logic / N. Takagi ; K. Nakashima
Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic / T. Ninomiya ; M. Mukaidono
On Urquhart's C Logic / A. Ciabattoni
Fuzzy Logic / Session 5a：
A New Class of Fuzzy Modifiers / M. De Cock ; E. Kerre
Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases / K. Strehl ; C. Moraga ; K.-H. Temme ; R. Stankovic
On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach / H. Thiele
Reed-Muller Logic and Its Extensions / Session 5b：
Experiments on FPRM Expressions for Partially Symmetric Logic Functions / S. Yanushkevich ; J. Butler ; G. Dueck ; V. Shmerko
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams / H. Babu
A New Algorithm to Compute Quaternary Reed-Muller Expansions
Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems / A. StoicaSession 6：
Logic and Algebra / Session 7a：
De Morgan Bisemilattices / J. Brzozowski
Finite-Valued Approximations of Product Logic / S. Aguzzoli ; B. Gerla
Integration of Information in Four-Valued Logics under Non-Uniform Assumptions / Y. Loyer ; N. Spyratos ; D. Stamate
Decision Diagrams / Session 7b：
Lower Bound Sifting for MDDs / D. Jankovic ; W. Gunther
Implementation of Multiple-Output Functions Using PQMDDs / Y. Iguchi ; M. Matsuura
Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams / M. Stankovic ; J. Astola ; K. Egiazarian
Circuits I / Session 8a：
Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits / M. Abd-El-Barr ; A. Al-Mutawa
Implementation of Multiple-Valued Multiplier on GF(3[subscript m]) Using Current Mode CMOS / H. Seong ; J. Choi ; B. Shin
Novel II-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic / X. Wu ; X. Zhou
Decision Diagrams and Test / Session 8b：
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions / H. Sack ; E. Dubrova ; C. Meinel
Dynamic Re-Encoding During MDD Minimization / F. Schmiedle
Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm / N. Kamiura ; Y. Hata ; N. Matsui
Evolutionary and Information Theory Approaches / Session 9a：
Evolutionary Multi-Level Network Synthesis in Given Design Style / T. Luba ; M. Opoka
An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations / T. Hozumi ; O. Kakusho ; K. Yamato
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4) / D. Popel ; V. Cheushev
Image and Language Processing / Session 9b：
On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic / S. Kobashi ; Y. Kitamura ; T. Yanagida
Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra / L.-S. Lim
A Four-Valued Logic B(4) of E(9) for Modeling Human Communication / D. Rine ; R. Alnakari
Structures with Many-Valued Information and Their Relational Proof Theory / I. Duntsch ; W. MacCaull ; E. OrlowskaSession 10：
Circuits II / Session 11a：
Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop / T. Uemura ; T. Baba
A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation / G.-N. Byun ; C.-U. Lee ; S.-Y. Park ; H.-S. Kim
Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection / T. Waho ; K. Hattori ; K. Honda
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices / A. Gonzalez ; M. Bhattacharya ; S. Kulkarni ; P. Mazumder
Theorem-Proving and Applications / Session 11b：
The 2-SAT Problem of Regular Signed CNF Formulas / B. Beckert ; R. Hahnle ; F. Manya
Chaining Techniques for Automated Theorem Proving in Many-Valued Logics / H. Ganzinger ; V. Sofronie-Stokkermans
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables / T. Aoki ; K. Nakazawa ; T. Higuchi
Properties of Independent Components of Self-Motion Optical Flow / M. Jabri ; K.-Y. Park ; S.-Y. Lee ; T. SejnowskiSession 12：
Panel Discussion / Session 13：
Multiple-Valued Logic: Provocative Questions / D. Hammerstrom M. Kameyama ; R. Baltar ; Y. Takahashi
A Multilevel-Cell 32MB Flash Memory / M. Bauer ; R. Alexis ; G. Atwood ; B. Baltar ; A. Fazio ; K. Frary ; M. Hensel ; M. Ishac ; J. Javanifard ; M. Landgraf ; D. Leak ; K. Loe ; D. Mills ; P. Ruby ; R. Rozman ; S. Sweha ; S. Talreja ; K. WojciechowskiSession 14：
Circuits III / Session 15a：
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts / D. Olson ; K. Current
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels / T. Hanyu ; T. Ike ; M. Kameyama
Clones and Asynchronous Machines / Session 15b：
Rigidity Problem of Autodual Clones / M. Miyakawa ; I. Rosenberg
On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones / L. Haddad ; H. Machida
Logic Synthesis of Controllers for B-Ternary Asynchronous Systems / Y. Nagata ; D. Miller
Silicon Single-Electron Devices and Their Applications / A. Fujiwara ; Y. Ono ; K. MuraseSession 16：
Arithmetics and Systems / Session 17a：
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage / H. Kimura
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access / Y. Yuminaka ; O. Katoh ; Y. Sasaki
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic / S. Kaeriyama
Verification and Power Estimation / Session 17b：
A Method for Approximate Equivalence Checking
Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic / M. Pedram
Probabilistic Verification of Multiple-Valued Functions
Author Index
Message from the Symposium Chair
Message from the Co-Chairs
Reviewers
4.

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図書
4. Proceedings : 1998 28th IEEE International Symposium on Multiple-Valued Logic, May 27-29, 1998, Fukuoka, Japan (: paper ; : case)
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Japan Research Group on Multiple-Valued Logic
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c1998  xvi, 384 p. ; 28 cm
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5.

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5. Proceedings : the Thirteenth International Symposium on Multiple-Valued Logic, May 23-25, 1983, Holiday Inn, Kyoto, Japan
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Silver Spring, MD : IEEE Computer Society Press, c1983  xii, 431 p. ; 28 cm
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6.

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6. Proceedings : 1997 27th International Symposium on Multiple-Valued Logic :May 28-30, 1997, Antigonish, Nova Scotia, Canada (: paper ; : case.)
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, St. Francis Xavier University ; in cooperation with IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1997  x, 293 p. ; 28 cm
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7.

図書
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7. Proceedings 1996 26th International Symposium on Multiple-Valued Logic : May 29-31, 1996, Santiago de Compostela, Spain (: soft. ; : case.)
sponsored by IEEE Computer Society Technical Committee on Multiple-Value Logic, University of Satiago de Compostela ; in cooperation with IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1996  xii, 308 p. ; 28 cm
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8.

図書
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8. Proceedings 1995 25th International Symposium on Multiple-Valued Logic : May 23-25, 1995, Bloomington, Indiana (softbound ; casebound ; microfiche)
sponsored by IEEE Computer Society Technical Committee on Multiple-Value Logic, Indiana University in cooperation with IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1995  xii, 296 p. ; 28 cm
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9.

図書
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9. Proceedings : the Sixteenth International Symposium on Multiple-Valued Logic, May 27-29, 1986, Blacksburg, Virginia (: pbk. ; : hard)
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Washington, D.C. : IEEE Computer Society Press, c1986  xi, 289 p. ; 28 cm
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10.

図書
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10. Proceedings of the Twenty-first International Symposium on Multiple-Valued Logic : May 26-29, 1991, Victoria, B.C., Canada (pbk ; case ; microfiche)
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1991  xi, 383 p. ; 28 cm
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11.

図書
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11. Proceedings : the Twenty-Second International Symposium on Multiple-Valued Logic : May 27-29, 1992, Sendai, Japan (pbk ; case ; microfiche)
sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Multiple-Valued Logic, Japan Research Group on Multiple-Valued Logic
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1992  xv, 482 p. ; 28 cm
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12.

図書
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12. Proceedings : the Twentieth International Symposium on Multiple-Valued Logic, May 23-25, 1990, Charlotte, N.C. USA (pbk ; case)
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1990  xiv, 438 p. ; 28 cm
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13.

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13. Proceedings of the sixth International Symposium on Multiple-Valued Logic : May 25-28, 1976, University Center, Utah State University, Logan, Utah
International Symposium on Multiple-Valued Logic
出版情報: [s.l.] : IEEE, c1976  vii, 272 p. ; 28 cm
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14.

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14. Proceedings : the Tenth International Symposium on Multiple-Valued Logic, Northwestern University, Evanston, IL (: pbk)
International Symposium on Multiple-Valued Logic
出版情報: New York : the Institute of Electrical and Electronics Engineers, 1980  277 p. ; 28 cm
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15.

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15. Proceedings : the Nineteenth International Symposium on Multiple-Valued Logic, May 29-31, 1989, Guangzhou, China (: pbk. ; : case)
International Symposium on Multiple-Valued Logic ; IEEE Computer Society
出版情報: Washington, D.C. ; Tokyo : IEEE Computer Society Press, c1989  xv, 464 p. ; 28 cm
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16.

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16. Proceedings : the Twenty-Fourth International Symposium on Multiple-Valued Logic : May 25-27, 1994, Boston, Massachusetts (paper ; case)
sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Massachusetts at Boston
出版情報: Los Alamitos, Calif. ; Tokyo : IEEE Computer Society Press, c1994  xii, 368 p. ; 28 cm
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17.

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17. Proceedings : the Twenty-Third International Symposium on Multiple-Valued Logic : May 24-27, 1993, Sacramento, California (paper ; microfiche ; case)
sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Multiple-Valued Logic, Center for Image Processing and Integrated Computing at University of California, Davis
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1993  xii, 288 p. ; 28 cm
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18.

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18. Proceedings : 33rd IEEE International Symposium on Multiple-Valued Logic, 16-19 May, 2003, Meiji University, Tokyo, Japan
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Japanese Research Group on Multiple-Valued Logic, Meiji University
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xiv, 398 p. ; 28 cm
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目次情報: 続きを見る
Message from the Symposium Chair
Message from the Program Committee
Symposium Committee
Referees
Invited Address / Session 1：
Fuzzy Logic as a Basis for a Theory of Hierarchical Definability (THD) / L. Zadeh
Logic Design I / Session 2A：
Implementation of Multiple-Valued Functions Using Literal-Splitting Technique / E. Dubrova
Hyperoperations on {0, 1, 2} Based on Min, Max, and Universal Literal Operations / N. Takagi ; K. Nakashima
An Extension of Ternary Majority Function and Its Application to Evolvable System / Y. Yamamoto
A New Construction of the Irreducible Polynomial for Parallel Multiplier over GF(2[superscript m]) / J.-H. Hwang ; K.-J. Moon ; S.-Y. Park ; H.-S. Kim
Functional Expressions / Session 2B：
New Information on the Effectiveness of Different Reed-Muller Algebras on the Representation of Quaternary Functions / K. Adams ; J. McGregor
Polynomial Expansions over GF(3) Based on Fastest Transformation / B. Falkowski ; C. Fu
The Generation Circulation Method to Generalized Reed-Muller Coefficients over GF(3) / C. Lee ; G.-Y. Byun ; B.-S. Shin ; J.-H. Sim
Optimization of GF(4) Expressions Using the Extended Dual Polarity Property / D. Jankovic ; R. Stankovic ; C. Moraga
Fuzzy Logic / Session 3A：
Normal Forms for Fuzzy Logic Functions / I. Perfilieva
Towards Fuzzy Type Theory / V. Novak
Universes of Fuzzy Sets--A Short Survey / S. Gottwald
Fixed Points for Fuzzy Rule Bases and Fuzzy Chaining Syllogism / K. Soleimani ; M. Mashinchi ; H. Maleki
Automated Finding of the Willis Ring in MR Angiography Images Using Fuzzy Knowledge Base / S. Kobashi ; K. Kondo ; Y. Hata
LSI Design / Session 3B：
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms / J. Sakiyama ; T. Aoki ; T. Higuchi
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic / T. Hanyu ; T. Takahashi ; M. Kameyama
MVL Circuit Design and Characterization at the Transistor Level Using SUS-LOC / E. Kinvi-Boh ; M. Aline ; O. Sentieys ; E. Olson
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-valued Multiple-Output Logic Circuits / H. Babu ; Md. R. Islam ; A. Ali ; Md. M. Akon ; Md. A. Rahaman ; Md. F. Islam
Recursive Evaluation of the Generalized Reed-Muller Coefficients / G. Na ; S. Kim ; J. Choi ; H. Kim
Logic Design II / Session 4A：
Cascade Realizations of Two-Valued Input Multiple-Valued Output Functions Using Decomposition of Group Functions / T. Sasao
A Novel Technology Mapping Method for AND/XOR Expressions / S.-B. Ko ; J.-C. Lo
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space / A. Al-Rabadi
Multi-output Galois Field Sum of Products Synthesis with New Quantum Cascades / M. Khan ; M. Perkowski ; P. Kerntopf
Relationship between UCHT and FFT / S. Xie ; S. Rahardja ; Z. Gu
Logics and Algebras / Session 4B：
Several Remarks on Non-Boolean Functions over Boolean Algebras / D. Simovici
Complete and Independent Sets of Axioms of Boolean Algebra / T. Ninomiya ; M. Mukaidono
Characterization of the Axiomatizable Prenex Fragments of First-Order Godel Logics / M. Baaz ; N. Preining ; R. Zach
New Logical and Complexity Results for Signed-SAT / C. Ansotegui ; F. Manya
From Intuitionistic Logic to Godel-Dummett Logic via Parallel Dialogue Games / C. Fermuller ; A. Ciabattoni
Biomorphic Analog Devices Based on Reaction-Diffusion Systems / T. Asai ; Y. AmemiyaSession 5：
LSI Circuits / Session 6A：
Multiple-Valued Dynamic Source-Coupled Logic / A. Mochizuki
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic / K. Degawa
A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator / S. Han ; Y. Choi ; H. Seong
A Novel Multiple-Input Multiple-Valued Semi-floating-gate Latch / O. Mirmotahari ; Y. Berg
Decision Diagrams I / Session 6B：
On the Size of Multiple-Valued Decision Diagrams / D. Miller ; G. Dueck
Efficient Minimization of Multiple-Valued Decision Diagrams for Incompletely Specified Functions / D. Popel ; R. Drechsler
Compact Representations of Logic Functions Using Heterogeneous MDDs / S. Nagayama
Complexity of Decision Trees for Boolean Functions / R. Freivalds ; M. Miyakawa ; I. Rosenberg
Nano Technology / Session 7A：
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic / H. Inokawa ; Y. Takahashi
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-valued Logic / K.-W. Song ; S. Lee ; D. Kim ; K. Kim ; J. Kyung ; G. Baek ; C.-A. Lee ; J. Lee ; B.-G. Park
Proposal of Four-Valued MRAM Based on MTJ/RTD Structure / T. Uemura ; M. Yamamoto
Modeling and Simulation / Session 7B：
Modeling Multi-valued Circuits in SystemC / D. Grosse ; G. Fey
Dynamic Reliability Indices for Multi-state System / E. Zaitseva
CTL Model-Checking over Logics with Non-classical Negations / M. Chechik ; W. MacCaull
Clone Theory / Session 8A：
On the Centralizers of Monoids in Clone Theory / H. Machida
Generation of the Post Lattice by Irreducible Clones / G. Pogosyan
On Intervals of Partial Clones of Boolean Partial Functions / L. Haddad ; G. Simons
Spectral Techniques / Session 8B：
Family of Fast Transforms over GF(3) Logic
Spectral Transforms of Mixed-Radix MVL Functions / M. Thornton
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation / R. Krenz ; A. Kuehlmann
Functions of Multiple-Valued Logic and the Complexity of Constraint Satisfaction: A Short Survey / A. Krokhin ; A. Bulatov ; P. JeavonsSession 9：
Applications / Session 10A：
Learning Subjective Probabilities from a Small Data Set / C. Huang
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques / S. Kinder
From Continuous to Multiple-Valued Data
Decision Diagrams II / Session 10B：
Augmented Sifting of Multiple-Valued Decision Diagrams
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions / J. Butler
Generalized Complex Spectral Decision Diagrams Using Unified Complex Hadamard Transform
Author Index
Message from the Symposium Chair
Message from the Program Committee
Symposium Committee
19.

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図書
19. Proceedings : 31st IEEE International Symposium on Multiple-Valued Logic, May 22-24, 2001, Warsaw, Poland
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, Institute of Computer Science Polish Academy of Sciences
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 380 p. ; 28 cm
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目次情報: 続きを見る
Preface
Symposium Organizers and Program Committee
Referees
Invited Address / Session 1：
Algebras for Hazard Detection / J. Brzozowski ; Z. Esik ; Y. Iland
Circuits I / Session 2a：
A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits / M. Abd-El-Barr ; A. Al-Mutawa
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources / T. Ike ; T. Hanyu ; M. Kameyama
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators / M. Inaba ; K. Tanno ; O. Ishizuka
Design and Verification of Systems / Session 2b：
An Application of Multiple-Valued Logic to Test Case Generation for Software System Functional Testing / M. Hu
Spectral Techniques in Binary and Multiple-Valued Switching Theory / M. Karpovsky ; R. Stankovic ; C. Moraga
Tunnelling Diode Technology / W. Prost ; U. Auer ; F-J. Tegude ; C. Pacha ; K. Goser ; R. Duschl ; K. Eberl ; O. SchmidtSession 3：
Circuits II / Session 4a：
Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology / I. Ben Dhaou ; E. Dubrova ; H. Tenhunen
A 4-Digit CMOS Quaternary to Analog Converter with Current Switch and Neuron MOS Down-Literal Circuit / S. Han ; Y. Choi ; H. Kim
Fuzzy Logics and Their Applications I / Session 4b：
On Some Classes of Fuzzy Information Relations / A. Radzikowska ; E. Kerre
On Complete Residuated Many-Valued Logics with T-Norm Conjunction / F. Esteva ; L. Godo
Circuits III / Session 5a：
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors / T. Uemura ; T. Baba
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-Valued Circuits / T. Waho ; K. Hattori ; Y. Takamatsu
The Use of Arithmetic Operators in a Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Architecture / H. Teng ; R. Bolton
Fuzzy Logics and Their Applications II / Session 5b：
Evaluation of Inconsistency in a 2-Way Fuzzy Adaptive System Using Shadowed Sets / E. Gurkan ; A. Erkmen ; I. Erkmen
Identification of Incompletely Specified Fuzzy Unate Logic Function / H. Kikuchi
Representation Theorems and the Semantics of (Semi)Lattice-Based Logics / V. Sofronie-StokkermansSession 6：
Tutorial / Session 7：
Tutorial: Complexity of Many-Valued Logics / R. Hahnle
Exploiting Polarity in Multiple-Valued Inference Systems / Z. StachniakSession 8：
Logic Design I / Session 9a：
Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity / A. Al-Rabadi ; M. Perkowski
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits / K. Shimabukuro ; C. Zukeran
Decomposition of Multi-Valued Functions into Min- and Max-Gates / C. Lang ; B. Steinbach
Automated Reasoning and Complexity I / Session 9b：
Cut-Elimination in a Sequents-of-Relations Calculus for Godel Logic / M. Baaz ; A. Ciabattoni ; C. Fermuller
Model Checking with Multi-Valued Temporal Logics / M. Chechik ; S. Easterbrook ; B. Devereux
Automated Reasoning with Ordinary Assertions and Default Assumptions / D. Van Heule ; A. Hoogewijs
Logic Design II / Session 10a：
Information Theory Method for Flexible Network Synthesis / V. Cheushev ; S. Yanushkevich ; V. Shmerko ; J. Kolodziejczyk
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic / T. Sasao
Two-Stage Exact Detection of Symmetries / A. Tomaszewska ; P. Dziurzanski
Automated Reasoning and Complexity II / Session 10b：
A Modular Reduction of Regular Logic to Classical Logic / R. Bejar ; F. Manya
Hypersequents as a Uniform Framework for Urquhart's C, MTL and Related Logics
Polynomial-Time Algorithms for Verification of Some Properties of k-Valued Functions Represented by Polynomials / S. Selezneva
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI / Session 11：
Computing Paradigms / Session 12a：
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing / M. Hiratsuka ; T. Aoki ; T. Higuchi
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation / M. Natsui
An Axiomatization of Generalized Entropy of Partitions / D. Simovici ; S. Jaroszewicz
MV Logics and Algebras I / Session 12b：
Many Valued Paraconsistent Logic / C. Morgan
On Logical Fiberings and Decomposition of Many-Valued Operations: A Brief Survey / J. Pfalzgraf
Relations between Clones and Full Monoids / H. Machida ; M. Miyakawa ; I. Rosenberg
Classical Gentzen-Type Methods in Propositional Many-Valued Logics / A. AvronSession 13：
Decision Diagrams / Session 14a：
Selection of Efficient Re-Ordering Heuristics for MDD Construction / F. Schmiedle ; W. Gunther ; R. Drechsler
Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies / M. Stankovic ; J. Astola ; K. Egiazarian
Design of Haar Wavelet Transforms and Haar Spectral Transform Decision Diagrams for Multiple-Valued Functions
Fuzzy Logics and Set Theories / Session 14b：
A Set Theory within Fuzzy Logic / P. Hajek ; Z. Hanikova
On a Kleenean Extension of Fuzzy Measure / T. Araki ; M. Mukaidono ; F. Yamamoto
On Axiomatic Characterization of Fuzzy Approximation Operators II. The Rough Fuzzy Set Based Case / H. Thiele
Neural Networks / Session 15a：
A Functional Manipulation for Improving Tolerance against Multiple-Valued Weight Faults of Feedforward Neural Networks / N. Kamiura ; Y. Taniguchi ; N. Matsui
Logic Circuit Diagnosis by Using Neural Networks / H. Tatsumi ; Y. Murai ; S. Tokumasu
The Designing and Training of a Fuzzy Neural Hamming Classifier / Q. Hua ; Q-L. Zhen
MV Logics and Algebras II / Session 15b：
Weierstrass Approximations by Lukasiewicz Formulas with One Quantified Variable / S. Aguzzoli ; D. Mundici
Composing Submonads / P. Eklund ; M. Galan ; J. Medina ; M. Ojeda-Aciego ; A. Valverde
A Method of Uncertainty Reasoning by Using Information / J. Ma ; J. Liu ; Y. Xu
Author Index
Preface
Symposium Organizers and Program Committee
Referees
20.

図書
図書
20. Proceedings : 32nd IEEE International Symposium on Multiple-Valued Logic, May 15-18, 2002, Boston, Massachusetts, USA
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Massachusetts, Boston
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xi, 289 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chair
Message from the Program Committee
Reviewers
Invited Talk
Equations in the Algebra of Logic / S. Rudeanu
Algebra I
Some Results on the Centralizers of Monoids in Clone Theory / H. Machida ; I. Rosenberg ; M. Miyakawa
Partial Hyperclones on a Finite Set / B. Romov
On the Structures of Weak Interlaced Bilattice / M. Kondo
Logical Design I
Improving the Characterization of p-Valued Threshold Functions / C. Moraga
A Conjunctive Canonical Expansion of Multiple-Valued Functions / E. Dubrova ; P. Farm
Sierpinski Gaskets for Logic Functions Representation / D. Popel ; A. Dani
Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals / N. Takagi ; K. Nakashima
Circuits I
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI / Y. Yuminaka ; T. Morishita ; T. Aoki ; T. Higuchi
An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator / T. Waho ; S. Kobayashi ; K. Matsuura
Voltage Comparator Circuits for Multiple-Valued CMOS Logic / Y. Guo ; K. Current
Logical Design II
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions / D. Jankovic ; R. Stankovic ; R. Drechsler
Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results / K. Adams ; J. McGregor
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection / B. Polianskikh ; Z. Zilic
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis / M. Natsui
Consequence and Complexity in Infinite-Valued Logic: A Survey / V. Marra ; D. Mundici
Spectral Techniques
Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams / J. Astola
Chrestenson Spectrum Computation Using Cayley Color Graphs / M. Thornton ; D. Miller ; W. Townsend
The Role of Super-Fast Transforms in Speeding Up Quantum Computations / K. Radecka
Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images / B. Falkowski ; B. Olejnicka
Circuits II
Design of Dynamic Reliability Indices / E. Zaitseva ; V. Levashenko
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits / N. Kamiura ; T. Isokawa ; N. Matsui
Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics / X. Wu ; P. Wang ; Y. Xia
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition / H. Kimura ; T. Hanyu ; M. Kameyama
Optimization of Multi-Valued Multi-Level Networks / M. Gao ; J. Jiang ; Y. Jiang ; Y. Li ; A. Mishchenko ; S. Sinha ; T. Villa ; R. Brayton
Algebra II
de Morgan Bisemilattice of Fuzzy Truth Value / H. Kikuchi
Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra / T. Ninomiya ; M. Mukaidono
On Functions Defined on Free Boolean Algebras / D. Simovici ; S. Jaroszewicz
Logical Design III
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 1: LAR Based Model / S. Yanushkevich ; P. Dziurzanski ; V. Shmerko
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. Part 2: LWL Based Model / A. Tomaszewska
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics / I. Polian ; P. Engelke ; B. Becker
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms
Decision Diagrams
Variable Selection Heuristics and Optimum Decision Trees--An Experimental Study / N. Otsu
On the Construction of Multiple-Valued Decision Diagrams
Evaluation of Static Variable Ordering Heuristics for MDD Construction
Representations of Logic Functions Using QRMDDs / S. Nagayama ; T. Sasao ; Y. Iguchi ; M. Matsuura
Circuits III
Fully Source-Coupled Logic Based Multiple-Valued VLSI / T. Ike
A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block / S. Han ; S. Park ; H. Seong ; H. Kim
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits / M. Inaba ; K. Tanno ; O. Ishizuka
Author Index
Message from the General Chair
Message from the Program Committee
Reviewers
21.

図書
図書
21. Proceedings : the ninth International Symposium on Multiple-Valued Logic, the Beaufort Hotel, Bath, England, 1979 (: pbk)
International Symposium on Multiple-Valued Logic
出版情報: New York : the Institute of Electrical and Electronics Engineers, Inc., 1979  304 p. ; 28 cm
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22.

図書
図書
22. Proceedings, 35th International Symposium on Multiple-Valued Logic : May 19-21, 2005, University of Calgary, Calgary, Canada
sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xiv, 302 p. ; 28 cm
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23.

図書
図書
23. Proceedings : 34th International Symposium on Multiple-Valued Logic, University of Toronto, Toronto, Canada, May 19-22, 2004
[sponsored by IEEE Computer Society Technical Committee on Multiple-Valued Logic, University of Toronto, Altera Corporation]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2004  xiv, 353 p. ; 28 cm
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