| Preface |
| Plasma Processing for the 100 nm Node / Part I： |
| Plasma Processes |
| Kinetic Modeling for Multi-Component Thin Film Growth in Plasma-Enhanced Atomic Layer Deposition / J-H. Kim ; J-Y. Kim ; P-K. Park ; S-W. Kang |
| Incidence of Deposition Parameters on the Structural Properties of Y[subscript 2]O[subscript 3] Grown by Pulsed Injection PE-MOCVD / C. Durand ; C. Vallee ; O. Salicio ; V. Loup ; M. Bonavalot ; O. Joubert ; C. Dubourdieu |
| Copper-Barrier and Hard-Mask Elaboration by Plasma-Enhanced Chemical Vapor Deposition Using Organosilane Precursors / B. Remiat ; F. Fusalba ; P. Maury ; V. Jousseaume ; C. Lecornec ; F. Gaillard ; J. Durand |
| Gas-Phase and Surface Reactions in Plasma Enhanced Chemical Etching of High-k Dielectrics / L. Sha ; J.P. Chang |
| A Comparative Study of the Etching Behavior of Thin AlN and Al[subscript 2]O[subscript 3] Films / M. Engelhardt |
| Etching of Low-k Interconnect Materials for Next Generation Devices / T. Chevolleau ; N. Posseme ; L. Vallier ; I. Thomas-Boutherin |
| Resist Transformation during Etching Steps Involved in Patterning Low-k Dielectric Materials: Impact on Process Control / E. Pargon |
| Adhesion of Copper and Sulfur-Modified SiLK / D.-L. Bae ; J.J. Senkevich ; C. Kezewski ; Y. Kwon ; T.S. Cale |
| Porous SiOCH Modification Studies Induced by Ashing Processes / Thomas-Boutherin |
| Modeling Investigation of Plasma Clean Processes / D. Zhang ; D. Denning |
| Copper Interconnects with Low-k Inter Level Dielectric Films / Part II： |
| Copper Deposition |
| Preparation of Cu Films on Polymer Substrate by ECR-MOCVD Coupled with DC Bias at Room Temperature / J-K. Lee ; B-W. Cho |
| Effect of Novel Plasma Treatment on Superfilling Behavior in Chemically Enhanced CVD (CECVD) Cu Process / S-G. Pyo ; W-S, Min ; D-W. Lee ; S. Kim ; J-G. Lee |
| A Model of Copper Deposition for the Damascene Process / C. Gabrielli ; J. Kittel ; P. Mocoteguy ; H. Perrot ; A. Zdunek ; P. Bouard ; M. Haddix ; L. Doyen ; M.C. Clech |
| AFM Observation of Microstructural Evolution at Room Temperature in Electrodeposited Copper Metallization / S. Ahmed ; D.N. Buckley ; A. Arshak ; A.M. O'Connell ; L.D. Burke |
| "Seedless" Electrochemical Deposition of Copper on Liner-Materials for ULSI Devices / D.J. Duquette ; S.J. Kim ; M.J. Shaw |
| Electroless Metallization of Hydrogen-Terminated Si[left angle bracket]100[right angle bracket] Surface Functionalized by Viologen / W.H. Yu ; E.T. Kang ; K.G. Neoh |
| Barrier and Low-k Films |
| TiZrN as a Copper Barrier for 0.13 [mu]m and 0.09 [mu]mTechnology Nodes / L. Swedberg ; C. Prindle |
| Nanostructured Ta-Si-N Thin Films as Diffusion Barriers between Cu and SiO[subscript 2] / L.W. Lai ; C.C. Chang ; J.S. Chen ; Y.K. Lin |
| Selectivity Studies on Tantalum Barrier Layer for Copper Chemical Mechanical Planarization / A. Vijayakumar ; T. Du ; K.B. Sundaram ; V. Desai |
| Investigation of Barrier Layers for Cu-Ultra Low-k Porous Polymer Integration / L.Y. Yang ; D.H. Zhang ; C.Y. Li ; P.D. Foo ; K. Prasad ; C.M. Tan |
| Atomic Layer Deposition of Ruthenium Glue Layer for Copper Damascene Interconnect / O-K. Kwon |
| Introducing Advanced ULK Dielectric Mateials in Interconnects: Performance and Integration Challenges / C. Le Cornec ; K. Haxaire ; T. Mourier ; P.H. Haumesser ; S. Maitrejean ; J. Simon ; A. Chabli ; G. Passemard |
| Surface Modification of Porous Low-k Dielectrics / Q.T. Le ; C.M. Whelan ; H. Struyf ; S.H. Brongersma ; T. Conard ; W. Boullart ; S. Vanhaelemeersch ; K. Maex |
| Structural and Electrical Characteristics of Low Dielectric Constant Porous Hydrogen Silsesquioxane for Cu Metallization / J.H. Wang ; P.T. Liu ; T.C. Chang ; W.J. Chen ; S.L. Cheng ; J.Y. Lin ; L.J. Chen |
| Nanoporous Low-k Polyimide Films Prepared from Poly(Amic Acid) with Grafted Poly(Acrylic Acid)/Poly (Ethylene Glycol) Side Chains / W.C. Wang ; C.K. Ong ; L.F. Chen |
| X-Ray Photoelectron Spectroscopic Study of Surface Modification of SiLK under UV-Irradiation / Y. Uchida ; T. Fukuda ; H. Yanazawa |
| Characteristics of Low-k Methyl-Silsesquiazane (MSZ) for CMP Process Using Oxygen Plasma Treatment / T.M. Tsai ; S.T. Yan ; Y.C. Chang ; H. Aoki ; T.Y. Tseng |
| Copper CMP and Reliability |
| Electrochemical Planarization of Copper |
| A Multiscale Mechanical CMP Model for Patterned Wafers / J. Seok ; C.P. Sukam ; A.T. Kim ; J.A. Tichy |
| The Roles of Complexing Agents on Copper CMP / G. Lim ; T.E. Kim ; J.-H. Lee ; J. Kim ; H.-W. Lee |
| The Effect of Inhibitor and Complexing Agents on Cu CMP / Y. Luo |
| Role of Oxidizer and Inhibitor on Chemical Mechanical Planarization of Copper / S.C. Kuiry ; S. Seal |
| Effect of Abrasive Particles on Chemical Mechanical Polishing Performance / D. Tamboli ; G. Banerjee ; S. Chang ; M. Waddell ; I. Butcher ; Q. Arefeen ; S. Hymes |
| Chemical Mechanical Planarization of Ruthenium for Capacitor Bottom Electrode in DRAM Technology / S-H. Lee ; Y-J. Kang ; J-G. Park ; S-I. Lee |
| Industry Challenges in Post-Etch Cleaning Chemistries for Advanced Copper/Low-k Applications / M.A. Fury |
| Cleaning of Copper Surface Using Vapor-Phase Organic Acids / T. Yagishita ; K. Ishikawa ; M. Nakamura |
| Time-Zero Failure Current Measurement for Early Monitoring of Defective Cu Lines at Wafer Level / J-H. Park ; B-T. Ahn |
| Annealing Characteristics of Copper Films for Power Device Applications / L. Castoldi ; S. Morin ; G. Visalli ; T. Fukada ; M. Ouaknine ; E.H. Roh ; W.S. Yoo |
| The Stability of Carbon-Doped Silicon Oxide Low Dielectric Constant Thin Films / Y.H. Wang ; R. Kumar |
| Nickel Silicide Formation Using a Stacked Hotplate-Based Low Temperature Annealing System / T. Murakami ; B. Froment ; V. Carron ; W-S. Yoo |
| 3-D Interconnects |
| 3-D Electromigration Modeling and Simulation in Aluminum-Silicon Dioxide and Copper-Low-k Multilevel Interconnects / V. Sukharev ; R. Choudhary ; C.W. Park |
| Transient Thermal and Mechanical Modeling of 3D-IC Structures / J. Zhang ; J.-Q. Lu ; R.J. Gutmann |
| 3D System-on-a-Chip Using Dielectric Glue Bonding and Cu Damascene Inter-Wafer Interconnects / A. Jindal ; J.J. McMahon ; K.-W. Lee ; R.P. Craft ; B. Altemus ; D. Cheng ; E. Eisenbraum |
| The Impact of Wafer-Level Layer Transfer on High Performance Devices and Circuits for 3D IC Fabrication / K.W. Guarini ; A.W. Topol ; M. Ieong ; K. Bernstein ; K. Xiu ; R.V. Joshi ; R. Yu ; L. Shi ; M.R. Newport ; D.V. Singh ; G.M. Cohen ; H.B. Pogge ; S. Purushothaman ; W.E. Haensch |
| Wafer Bonding and Thinning Integrity for 3D-IC Fabrication |
| Author Index |
| Subject Index |
| Preface |
| Plasma Processing for the 100 nm Node / Part I： |
| Plasma Processes |
図書
