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1.

図書

図書
edited by D. Dowson ... [et al.]
出版情報: Amsterdam ; Tokyo : Elsevier for the Institute of Tribology, Leeds University and the Institut national des sciences appliquees de Lyon, 1988  vii, 395 p. ; 31 cm
シリーズ名: Tribology series ; 12
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2.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Simulation, ACM Special Interest Group on Simulation (SIGSIM), Society for Computer Simulation
出版情報: Los Alamitos, CA : IEEE Computer Society, c1997  xii, 197 p. ; 28 cm
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3.

図書

図書
sponsored by Los Angeles and San Francisco Bay Area Councils, IEEE, and Southern and Northern California Chapter, ERA
出版情報: Piscataway, NJ : Institute of Electrical and Electronics Engineers, c1994  x, 694 p. ; 29 cm
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4.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Simulation, ACM Special Interest Group on Simulation (SIGSIM), Society for Computer Simulation
出版情報: Los Alamitos, CA : IEEE Computer Society Press, c1995  xi, 209 p. ; 28 cm
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5.

図書

図書
[sponsored by IEEE Computer Society, Technical Committee on Microprogramming and Microarchitecture (TC-MICRO), Association for Computing Machinery - SIGMICRO]
出版情報: New York : Association for Computing Machinery, c1994  viii, 233 p. ; 28 cm
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6.

図書

図書
sponsored by IEEE TC-MARCH, ACM SIGMICRO ; with the generous support of Intel, Microsoft, Hewlett-Packard, IBM, SGI
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1999  xiii, 299 p. ; 28 cm
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目次情報: 続きを見る
Foreword
Committees
Reviewers
Welcome and Keynote / Uri WeiserSession 1:
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies / F. Pollack
Faster FrontEnd / Gary TysonSession 2:
Control Independence in Trace Processors / E. Rotenberg ; J. Smith
Fetch Directed Instruction Prefetching / G. Reinman ; B. Calder ; T. Austin
Improving Branch Predictors by Correlating on Data Values / T. Heil ; Z. Smith
Instruction Fetch Mechanisms for Multipath Execution Processors / A. Klauser ; D. Grunwald
3D and MultiMedia / Matthew FarrensSession 3:
A Superscalar 3D Graphics Engine / A. Wolfe ; D. Noonburg
Dynamic 3D Graphics Workload Characterization and the Architectural Implications / T. Mitra ; T. Chiueh
Exploiting a New Level of DLP in Multimedia Applications / J. Corbal ; R. Espasa ; M. Valero
Efficient Embedded Processors / Kemal EbciogluSession 4:
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors / S. Larin ; T. Conte
Evaluation of a High Performance Code Compression Method / C. Lefurgy ; E. Piccininni ; T. Mudge
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops / L. Lee ; J. Scott ; B. Moyer ; J. Arends
Memory Hierarchy / Doug BurgerSession 5:
Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems / S. Abraham ; S. Mahlke
Hardware Identification of Cache Conflict Misses / J. Collins ; D. Tullsen
Access Region Locality for High-Bandwidth Processor Memory System Design / S. Cho ; P. Yew ; G. Lee
Code Transformations to Improve Memory Parallelism / V. Pai ; S. Adve
Better Scheduling / Stephan JourdanSession 6:
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results / D. Connors ; W. Hwu
Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing / S. Onder ; R. Gupta
Read-After-Read Memory Dependence Prediction / A. Moshovos ; G. Sohi
Delaying Physical Register Allocation through Virtual-Physical Registers / T. Monreal ; A. Gonzalez ; J. Gonzalez ; V. Vinals
Invited Speaker / Gabby SilbermanSession 7:
Core Technologies in Hardware and Software / B. Shriver
Novel Microarchitectures and Multithreading / Brad CalderSession 8:
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Exploiting ILP in Page-based Intelligent Memory / M. Oskin ; J. Hensley ; D. Keen ; F. Chong ; M. Farrens ; A. Chopra
The Use of Multithreading for Exception Handling / C. Zilles ; J. Emer
Value Prediction for Speculative Multithreaded Architectures / P. Marcuello ; J. Tubella
Low Power Enhancements / Mateo ValeroSession 9:
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors / E. Musoll
Selective Cache Ways: On-Demand Cache Resource Allocation / D. Albonesi
Compilers / David BernsteinSession 10:
Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs / J. Bharadwaj ; K. Menezes ; C. McKinsey
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks / A. Eichenberger ; W. Meleis
Optimizations and Oracle Parallelism with Dynamic Translation / K. Ebcioglu ; E. Altman ; S. Sathaye ; M. Gschwind
Summary and Awards / Session 11:
Index of Authors
Foreword
Committees
Reviewers
7.

図書

図書
sponsored by the ACM Special Interest Groups, SIGCOMM, SIGGRAPH, SIGMULTIMEDIA, and SIGMIS
出版情報: New York : Association for Computing Machinery, c1996  xiv, 457 p. ; 28 cm
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8.

図書

図書
sponsored by Association for Computing Machinery Special Interest Group on Security, Audit, and Control, with support from United States Department of Defense, University of Newcastle upon Tyne
出版情報: New York : Association for Computing Machinery, c1998  vi, 116 p. ; 28 cm
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9.

図書

図書
Co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microarchitecture
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1998  xiv, 317 p. ; 28 cm
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10.

図書

図書
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  xi, 291 p. ; 28 cm
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目次情報: 続きを見る
General Chair's Message
Program Chair's Message
Conference Organization
Reviewers
Plenary Session
Opening Remarks
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1:
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2:
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3:
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4:
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5:
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A:
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B:
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7:
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8:
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
Author Index
General Chair's Message
Program Chair's Message
Conference Organization
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