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1.

図書

図書
Warren A. Hunt Jr., Steven D. Johnson (eds.)
出版情報: Berlin : Springer, c2000  xi, 537 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 1954
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2.

図書

図書
Ganesh Gopalakrishnan, Phillip Windley, (eds.)
出版情報: Berlin ; New York : Springer, c1998  ix, 528 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 1522
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目次情報: 続きを見る
Minimalist Proof Assistants: Interactions of Technology an Methodology in Formal System Level Verification / Kenneth L. McMillan
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution / Robert B. Jones ; Jens U. Skakkebaek ; David L. Dill
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking / Miroslav N. Velev ; Randal E. Bryant
Solving Bit-Vector Equations / M.Oliver Moller ; Harald Rueß
The Formal Design of 1M-Gate ASICs / Asgeir Por Eiriksson
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations / Justin E. Harlow III ; Franc Brglez
A Tutorial on Stalmarck's Proof Procedure for Propositional Logic Mary Sheeran and Gunnar Stalmarck
Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods / Macha Nikolskaia ; Antoine Rauzy ; David James Sherman
Bisimulation Minimization in an Automata-Theoretic Verification Framework / Kathi Fisler ; Moshe Y. Vardi
Automatic Verification of Mixed-Level Logic Circuits / Keith Hanna
A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk / S. Tasiran ; S.P. Khatri ; S. Yovine ; R.K. Brayton ; A. Sangiovanni-Vincentelli
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints / Fen Jin ; Henrik Hulgaard ; Eduard Cerny
Using MTBDDs for Composition and Model Checking of Real-Time Systems / Jurgen Ruf ; Thomas Kropf
Formal Methods in CAD from an Industrial Perspective / Carl-Johan H. Seger
A Methodology for Automatic Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool / Nazanin Mansouri ; Ranga Vemuri
Combined Formal Post- and Presynthesis Verification in High Level Synthesis / Thomas Lock ; Michael Mendler ; Matthias Mutz
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem / Abdel Mokkedem ; Ravi Hosabettu ; Ganesh Gopalakrishnan
A Performance Study of BDD-Based Model Checking / Bwolen Yang ; David R. O'Hallaron ; Armin Biere ; Olivier Coudert ; Geert Janssen ; Rajeev K. Ranjan ; Fabio Somenzi
Symbolic Model Checking Visualization / Gila Kamhi ; Limor Fix ; Ziv Binyamini
Input Elimination and Abstraction in Model-Checking / Sela Mador-Haim
Symbolic Simulation of the JEM1 Microprocessor / David A. Greve
Symbolic Simulation: An ACL2 Approach / J. Strother Moore
Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study / Amir Pnueli ; T. Arons
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification / Sergey Berezin ; Edmund Clarke ; Yunshan Zhu
Formally Verifying Data and Control with Weak Reachability Invariants / Jeffrey Su
Generalized Reversible Rules / C. Norris Ip
An Assume-Guarantee Rule for Checking Simulation / Thomas A. Henzinger ; Shaz Qadeer ; Sriram K. Rajamani ; Serdar Tasiran
Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared / Sofiene Tahar ; Paul Curzon ; Jianping Lu
An Instruction Set Process Calculus / Shiu-Kai Chin ; Jang Dae Kim
Techniques for Implicit State Enumeration of EFSMs / James H. Kukula ; Tom R. Shiple ; Adnan Aziz
Model Checking on Product Structures / Klaus Schneider
BDDNOW: A Parallel BDD Package / Kim Milvang-Jensen ; Alan J. Hu
Model-Checking VHDL with CV / David Deharbe ; Subash Shankar ; Edmund M. Clarke
Alexandria: A Tool for Hierarchical Verification / Annette Bunker ; Trent N. Larson ; Michael D. Jones ; Phillip J. Windley
PV: An Explicit Enumeration Model-Checker / Ratan Nalumasu
Author Index
Minimalist Proof Assistants: Interactions of Technology an Methodology in Formal System Level Verification / Kenneth L. McMillan
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution / Robert B. Jones ; Jens U. Skakkebaek ; David L. Dill
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking / Miroslav N. Velev ; Randal E. Bryant
3.

図書

図書
Mandayam Srivas, Albert Camilleri (eds.)
出版情報: Berlin : Springer, c1996  ix, 470 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 1166
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4.

図書

図書
Ramayya Kumar, Thomas Kropf (eds.)
出版情報: Berlin : Springer, c1995  viii, 303 p. ; 24 cm
シリーズ名: Lecture notes in computer science ; 901
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5.

図書

図書
edited by V. Stavridou, T.F. Melham, R.T. Boute
出版情報: Amsterdam ; New York : North-Holland, 1992  360 p.
シリーズ名: IFIP transactions ; A . Computer science and technology ; 10
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