National Conference on Fluid Power ; Illinois Institute of Technology ; IIT Research Institute ; National Fluid Power Association ; Fluid Power Society
World Maritime Technology Conference ; International Co-operation on Marine Engineering Systems ; International Naval Engineering Conference ; Advanced Technologies in Underwater Vehicles Conference ; International Marine Renewable Energy Conference
editor, B. Morrison ; sponsor, the International Association of Science and Technology for Development (IASTED) . editor, M. H. Hamza ; sponsor, the International Association of Science and Technology for Development (IASTED) Technical Committee on Robotics Technical Committee on Telecommunications, International Journal of Robotics and Automation
出版情報:
Anaheim, Calif. : ACTA Press, c2011 vi, 485 p. ; 28 cm
Keynote Speech: Greg Papadopoulos, CTO, Sun Microsystems Inc., USA
Multithreading and Speculation / Session 1：
Execution-based Prediction Using Speculative Slices / C. Zilles ; G. Sohi
Speculative Precomputation: Long-range Prefetching of Delinquent Loads / J. Collins ; H. Wang ; D. Tullsen ; C. Hughes ; Y. Lee ; D. Lavery ; J. Shen
Dynamically Allocating Processor Resources between Nearby and Distant ILP / R. Balasubramonian ; S. Dwarkadas ; D. Albonesi
Memory System Issues / Session 2：
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors / C. Luk
Data Prefetching by Dependence Graph Precomputation / M. Annavaram ; J. Patel ; E. Davidson
Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? / V. Cuppu ; B. Jacob
Processor Architecture / Session 3：
Focusing Processor Policies via Critical-Path Prediction / B. Fields ; S. Rubin ; R. Bodik
Automated Design of Finite State Machine Predictors for Customized Processors / T. Sherwood ; B. Calder
Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction / Y. Wu ; D. Chen ; J. Fang
Communication Support / Session 4：
CryptoManiac: A Fast Flexible Architecture for Secure Communication / L. Wu ; C. Weaver ; T. Austin
QoS Provisioning in Clusters: An Investigation of Router and NIC Design / K. Yum ; E. Kim ; C. Das
Cache Management / Session 5：
Locality vs. Criticality / S. Srinivasan ; R. Ju ; A. Lebeck ; C. Wilkerson
Dead-Block Prediction and Dead-Block Correlating Prefetchers / A. Lai ; C. Fide ; B. Falsafi
Code Layout Optimizations for Transaction Processing Workloads / A. Ramirez ; L. Barroso ; K. Gharachorloo ; R. Cohn ; J. Larriba-Pey ; P. Lowney ; M. Valero
Architectural Impact of Emerging Technologies / Session 6A：
Exploring and Exploiting Wire-Level Pipelining in Emeging Technologies / M. Niemier ; P. Kogge
NanoFabrics: Spatial Computing Using Molecular Electronics / S. Goldstein ; M. Budiu
Shared-Memory Multiprocessors / Session 6B：
A Simple Method for Extracting Models from Protocol Code / D. Lie ; A. Chou ; D. Engler ; D. Dill
Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization / M. Prvulovic ; M. Garzaran ; L. Rauchwerger ; J. Torrellas
Energy-Effective Designs / Session 7：
Power and Energy Reduction Via Pipeline Balancing / R. Bahar ; S. Manne
Energy-Effective Issue Logic / D. Folegnani ; A. Gonzalez
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power / S. Kaxiras ; Z. Hu ; M. Martonosi
Performance Tools and Evaluations / Session 8：
Variability in the Execution of Multimedia Applications and Implications for Architecture / P. Kaul ; S. Adve ; R. Jain ; C. Park ; J. Srinivasan
Measuring Experimental Error in Microprocessor Simulation / R. Desikan ; D. Burger ; S. Keckler
Rapid Profiling via Stratified Sampling / S. Sastry ; J. Smith
Thermal and Energy-Aware Microarchitectures / Session 1：
Temperature-Aware Microarchitecture / K. Skadron ; M. Stan ; W. Huang ; S. Velusamy ; K. Sankaranarayanan ; D. Tarjan
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor / G. Magklis ; M. Scott ; G. Semeraro ; D. Albonesi ; S. Dropsho
Processor Architecture / Session 2：
Half-Price Architecture / I. Kim ; M. Lipasti
Implicitly-Multithreaded Processors / I. Park ; B. Falsafi ; T. Vijaykumar
Panel: Subsetting SPEC When Measuring Results: Valid or Manipulative?
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences / D. Citron
Microarchitecture Techniques / Session 3a：
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors / J. Tseng ; K. Asanovic
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage / M. Powell
Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling / R. Wunderlich ; T. Wenisch ; J. Hoe
Recovery and Replay / Session 3b：
Transient-Fault Recovery for Chip Multiprocessors / M. Gomaa ; C. Scarbrough ; I. Pomeranz
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes / M. Prvulovic ; J. Torrellas
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay / M. Xu ; R. Bodik ; M. Hill
Energy-Saving Designs / Session 4a：
A Highly-Configurable Cache Architecture for Embedded Systems / C. Zhang ; F. Vahid ; W. Najjar
Energy Efficient Co-Adaptive Instruction Fetch and Issue / A. Buyuktosunoglu ; T. Karkhanis ; P. Bose
Positional Adaptation of Processors: Application to Energy Reduction / M. Huang ; J. Renau
DRPM: Dynamic Speed Control for Power Management in Server Class Disks / S. Gurumurthi ; A. Sivasubramaniam ; M. Kandemir ; H. Franke
Interconnects and Multiprocessors / Session 4b：
Token Coherence: Decoupling Performance and Correctness / M. Martin ; D. Wood
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks / A. Singh ; W. Dally ; A. Gupta ; B. Towles
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors / P. Harper ; D. Sorin
Performance Analysis of the Alpha 21364-Based HP GS1280 Multiprocessor / Z. Cvetanovic
Front-End Scheduling / Session 5：
Parallelism in the Front-End / P. Oberoi ; G. Sohi
Effective ahead Pipelining of Instruction Block Address Generation / A. Seznec ; A. Fraboulet
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay / D. Ernst ; A. Hamel ; T. Austin
Clustered Processors / Session 6a：
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors / R. Bhargava ; L. John
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors / R. Balasubramonian ; S. Dwarkadas
A Pipelined Memory Architecture for High Throughput Network Processors / T. Sherwood ; G. Varghese ; B. Calder
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput / J. Hasan ; S. Chandra
Prediction / Session 7a：
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History / R. Thomas ; M. Franklin ; C. Wilkerson ; J. Stark
Detecting Global Stride Locality in Value Streams / H. Zhou ; J. Flanagan ; T. Conte
Phase Tracking and Prediction / S. Sair
Mechanisms and Support / Session 7b：
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems / A. Anantaraman ; K. Seth ; K. Patil ; E. Rotenberg ; F. Mueller
DISE: A Programmable Macro Engine for Customizing Applications / M. Corliss ; E. Lewis ; A. Roth
Building Quantum Wires: The Long and the Short of It / M. Oskin ; F. Chong ; I. Chuang ; J. Kubiatowicz
Memory Issues / Session 8：
Guided Region Prefetching: A Cooperative Hardware/Software Approach / Z. Wang ; D. Burger ; S. Reinhardt ; K. McKinley ; C. Weems
Overcoming the Limitations of Conventional Vector Processors / C. Kozyrakis ; D. Patterson
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels / J. Suh ; E. Kim ; S. Crago ; L. Srinivasan ; M. French
Exploiting Parallelisms / Session 9：
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture / K. Sankaralingam ; R. Nagarajan ; H. Liu ; C. Kim ; J. Huh ; S. Keckler ; C. Moore
The Jrpm System for Dynamically Parallelizing Java Programs / M. Chen ; K. Olukotun
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