| Message from the Symposium Chairs |
| Organizing Committee |
| Program Committee |
| Yield I / Session 1： |
| Manufacturability Analysis of Analog CMOS ICs Through Examination of Multiple Layout Solutions / P. Khademsameni ; M. Syrzycki |
| Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI / A. Vassighi ; O. Semenov ; M. Sachdev ; A. Keshavarzi |
| Yield Estimates for the TESH Multicomputer Network / B. M. Maziarz ; V. K. Jain |
| Crosstalk Faults / Session 2： |
| A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis / P. Civera ; L. Macchiarulo ; M. Violante |
| A Test-Vector Generation Methodology for Crosstalk Noise Faults / H. Hashempour ; Y.-B. Kim ; N. Park |
| Self-Checking and ABFT / Session 3： |
| A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard / G. Bertoni ; L. Breveglieri ; I. Koren ; P. Maistri ; V. Piuri |
| Designing Self-Checking FPGAs Through Error Detection Codes / C. Bolchini ; F. Salice ; D. Sciuto |
| Self-Checking 1-out-of-n CMOS Current-Mode Checker / J. Mathew ; E. Dubrova |
| Partially Duplicated Code-Disjoint Carry-Skip Adder / D. Marienfeld ; V. Ocheretnij ; M. Gossel ; E. S. Sogomonyan |
| Input Ordering in Concurrent Checkers to Reduce Power Consumption / K. Mohanram ; N. A. Touba |
| Fault Simulation and Injection I / Session 4： |
| New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs / D. Alexandrescu ; L. Anghel ; M. Nicolaidis |
| Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied / R. Velazco ; A. Corominas ; P. Ferreyra |
| Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm / H.-B. Wang ; S.-Y. Huang ; J.-R. Huang |
| Scan Design / Session 5： |
| Scan Architecture for Shift and Capture Cycle Power Reduction / P. M. Rosinger ; B. M. Al-Hashimi ; N. Nicolici |
| Inserting Test Points to Control Peak Power During Scan Testing / R. Sankaralingam |
| Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits / C.-H. Cheng |
| Test Application / Session 6： |
| Matrix-Based Test Vector Decompression Using an Embedded Processor / K. J. Balakrishnan |
| Data Compression for System-on-Chip Testing Using ATE / F. Karimi ; W. Meleis ; Z. Navabi ; F. Lombardi |
| Test Generation / Session 7： |
| Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-At and Transition Faults / J. Dworak ; J. Wingfield ; B. Cobb ; S. Lee ; L.-C. Wang ; M. R. Mercer |
| Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE / F. J. Meyer |
| Testing Digital Circuits with Constraints / A. A. Al-Yamani ; S. Mitra ; E. J. McCluskey |
| Concurrent Error Detection / Session 8： |
| On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits / C. Metra ; S. Di Francescantonio ; G. Marrale |
| Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling / F. M. Goncalves ; M. B. Santos ; I. C. Teixeira ; J. P. Teixeira |
| A Memory Overhead Evaluation of the Interleaved Signature Instruction Stream / F. Rodriguez ; J. C. Campelo ; J. J. Serrano |
| Fault-Tolerant CAM Architectures: A Design Framework / M. G. Sami ; R. Stefanelli |
| Fault Simulation and Injection II / Session 9： |
| Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes / L. Antoni ; R. Leveugle ; B. Feher |
| A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques / S. Blanc ; J. Gracia ; P. J. Gil |
| Fault List Compaction Through Static Timing Analysis for Efficient Fault Injection Experiments / M. Sonza Reorda |
| Interconnect / Session 10： |
| Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH / S. Horiguchi ; Y. Miura |
| Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations / X. Sun ; A. Alimohammad ; P. Trouborst |
| Testing Layered Interconnection Networks |
| Yield II / Session 11： |
| Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure / Y. Hamamura ; K. Nemoto ; T. Kumazawa ; H. Iwata ; K. Okuyama ; S. Kamohara ; A. Sugimoto |
| Yield Modeling of a WSI Telcom Router Architecture / B. Qiu ; Y. Savaria ; M. Lu ; C. Wang ; C. Thibeault |
| System-on-Chip Test / Session 12： |
| Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation / O. Sinanoglu ; A. Orailoglu |
| Adaptive Test Scheduling in SoC's by Dynamic Partitioning / D. Zhao ; S. Upadhyaya |
| Feasibility of CED / Session 13： |
| Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies / T. Verdel ; Y. Makris |
| Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage / S. J. Piestrak |
| Test / Session 14： |
| Emulation-Based Design Errors Identification / A. CasteInuovo ; A. Fin ; F. Fummi ; F. Sforza |
| A New Functional Fault Model for FPGA Application-Oriented Testing / M. Rebaudengo |
| Neighbor Current Ratio (NCR): A New Metric for I[subscript DDQ] Data Analysis / S. S. Sabade ; D. M. H. Walker |
| CMOS Standard Cells Characterization for I[subscript DDQ] Testing / W. A. Pleskacz ; T. Borejko ; W. Kuzmicz |
| On-Chip Jitter Measurement for Phase Locked Loops / T. Xia ; J.-C. Lo |
| Neural Networks-Based Parametric Testing of Analog IC / V. Stopjakova ; D. Micusik ; L. Benuskova ; M. Margala |
| Reliable and Repairable Memories / Session 15： |
| Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems / M. Choi ; Y. B. Kim |
| Repairability Evaluation of Embedded Multiple Region DRAMs / Y. Chang |
| Author Index |
| TTTC Information |
| Message from the Symposium Chairs |
| Organizing Committee |
| Program Committee |
図書
