Fundamentals of Computer Design / Chapter 1: |
Introduction / 1.1: |
The Changing Face of Computing and the Task of the Computer Designer / 1.2: |
Technology Trends / 1.3: |
Cost, Price, and their Trends / 1.4: |
Measuring and Reporting Performance / 1.5: |
Quantitative Principles of Computer Design / 1.6: |
Putting It All Together: Performance and Price-Performance / 1.7: |
Another View: Power Consumption and Efficiency as the Metric / 1.8: |
Fallacies and Pitfalls / 1.9: |
Concluding Remarks / 1.10: |
Historical Perspective and References Exercises / 1.11: |
Instruction Set Principles and Examples / Chapter 2: |
Classifying Instruction Set Architectures / 2.1: |
Memory Addressing / 2.3: |
Addressing Modes for Signal Processing / 2.4: |
Type and Size of Operands / 2.5: |
Operands for Media and Signal Processing / 2.6: |
Operations in the Instruction Set / 2.7: |
Operations for Media and Signal Processing / 2.8: |
Instructions for Control Flow / 2.9: |
Encoding an Instruction Set / 2.10: |
Crosscutting Issues: The Role of Compilers / 2.11: |
Putting It All Together: The MIPS Architecture / 2.12: |
Another View: The Trimedia TM32 CPU / 2.13: |
Instruction-Level Parallelism and its Dynamic Exploitation / 2.14: |
Instruction-Level Parallelism: Concepts and Challenges / 3.1: |
Overcoming Data Hazards with Dynamic Scheduling / 3.2: |
Dynamic Scheduling: Examples and the Algorithm / 3.3: |
Reducing Branch Costs with Dynamic Hardware Prediction / 3.4: |
High Performance Instruction Delivery / 3.5: |
Taking Advantage of More ILP with Multiple Issue / 3.6: |
Hardware Based Speculation / 3.7: |
Studies of the Limitations of ILP / 3.8: |
Limitations on ILP for Realizable Processors / 3.9: |
Putting It All Together: The P6 Microarchitecture / 3.10: |
Another View: Thread Level Parallelism / 3.11: |
Crosscutting Issues: Using an ILP Datapath to Exploit TLP / 3.12: |
Exploiting Instruction Level Parallelism with Software Approaches / 3.13: |
Basic Compiler Techniques for Exposing ILP / 4.1: |
Static Branch Prediction / 4.2: |
Static Multiple Issue: the VLIW Approach / 4.3: |
Advanced Compiler Support for Exposing and Exploiting ILP / 4.4: |
Hardware Support for Exposing More Parallelism at Compile-Time / 4.5: |
Crosscutting Issues / 4.6: |
Putting It All Together: The Intel IA-64 Architecture and Itanium Processor / 4.7: |
Another View: ILP in the Embedded and Mobile Markets / 4.8: |
Memory-Hierarchy Design / 4.9: |
Review of the ABCs of Caches / 5.1: |
Cache Performance / 5.3: |
Reducing Cache Miss Penalty / 5.4: |
Reducing Miss Rate / 5.5: |
Reducing Cache Miss Penalty or Miss Rate via Parallelism / 5.6: |
Reducing Hit Time / 5.7: |
Main Memory and Organizations for Improving Performance / 5.8: |
Memory Technology / 5.9: |
Virtual Memory / 5.10: |
Protection and Examples of Virtual Memory / 5.11: |
Crosscutting Issues in the Design of Memory Hierarchies / 5.12: |
Putting It All Together: Alpha 21264 Memory Hierarchy / 5.13: |
Another View: The Emotion Engine of the Sony Playstation 2 / 5.14: |
Another View: The Sun Fire 6800 Server / 5.15: |
Multiprocessors and Thread-Level Parallelism / 5.16: |
Characteristics of Application Domains / 6.1: |
Symmetric Shared-Memory Architectures / 6.3: |
Performance of Symmetric Shared-Memory Multiprocessors / 6.4: |
Distributed Shared-Memory Architectures / 6.5: |
Performance of Distributed Shared-Memory Multiprocessors / 6.6: |
Synchronization / 6.7: |
Models of Memory Consistency: An Introduction / 6.8: |
Multithreading: Exploiting Thread-Level Parallelism within a Processor / 6.9: |
Putting It All Together: Sun''s Wildfire Prototype / 6.10: |
Another View: Multithreading in a Commercial Server / 6.12: |
Another View: Embedded Multiprocessors / 6.13: |
Historical Perspective and References Exercises Cha / 6.14: |
Fundamentals of Computer Design / Chapter 1: |
Introduction / 1.1: |
The Changing Face of Computing and the Task of the Computer Designer / 1.2: |