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図書

図書
edited by Shunri Oda, David K. Ferry
出版情報: Boca Raton : CRC Press, c2016  xii, 288 p. ; 24 cm
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図書

図書
S. Oda, D.F. Moore
出版情報: Cambridge : MTP, 2005  vi, 66 p. ; 30 cm
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図書

図書
editors, Markus Winterer ...[et al.]
出版情報: Warrendale, Pa. : Materials Research Society, c2010  xi, 159 p. ; 24 cm
シリーズ名: Materials Research Society symposium proceedings ; v. 1260
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図書

図書
W・マリ著 ; 小田俊理訳
出版情報: 東京 : 啓学出版, 1990.12  xii,331p ; 23cm
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図書

図書
森泉豊栄 [ほか] 編集
出版情報: 東京 : 朝倉書店, 2006.9  xii, 680p ; 22cm
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図書

図書
edited by Shunri Oda and David K. Ferry
出版情報: Boca Raton : Taylor & Francis Group, 2006  313 p. ; 24 cm
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目次情報: 続きを見る
Physics of Silicon Nanodevices / David K. Ferry ; Richard Akis ; Matthew J. Gilbert ; Stephen M. RameyChapter 1:
Introduction / 1.1:
Small MOSFETs / 1.2:
The Simple One-Dimensional Theory / 1.2.1:
Ballistic Transport in the MOSFET / 1.2.2:
Granularity / 1.3:
Quantum Behavior in the Device / 1.4:
The Effective Potential / 1.4.1:
Effective Carrier Wave Packet / 1.4.1.1:
Statistical Considerations / 1.4.1.2:
Quantum Simulations / 1.4.2:
The Device Structure / 1.4.2.1:
The Wave Function and Technique / 1.4.2.2:
Results / 1.4.2.3:
Quantum Dot Single-Electron Devices / 1.5:
Many-Body Interactions / 1.6:
Acknowledgments / 1.7:
References
Practical CMOS Scaling / David J. FrankChapter 2:
CMOS Technology Overview / 2.1:
Current CMOS Device Technology / 2.2.1:
International Technology Roadmap for Semiconductors (ITRS) Projections / 2.2.2:
Scaling Principles / 2.3:
General Scaling
Characteristic Scale Length / 2.3.2:
Exploratory Technology / 2.4:
New Materials / 2.4.1:
Fully Depleted SOI / 2.4.2:
Double-Gate and Multiple-Gate FET Structures / 2.4.3:
Limits to Scaling / 2.5:
Quantum Mechanics / 2.5.1:
Atomistic Effects / 2.5.2:
Thermodynamic Effects / 2.5.3:
Practical Considerations / 2.5.4:
Power-Constrained Scaling Limits / 2.6:
Summary / 2.7:
The Scaling Limit of MOSFETs due to Direct Source-Drain Tunneling / Hisao KawauraChapter 3:
EJ-MOSFETs / 3.1:
Concept of EJ-MOSFETs / 3.2.1:
Fabrication of the Device Structure / 3.2.2:
Basic Operation / 3.2.3:
Direct Source-Drain Tunneling / 3.3:
Detection of the Tunneling Current / 3.3.1:
Numerical Study of the Tunneling Current / 3.3.2:
The Scaling Limit of MOSFETs / 3.4:
Estimation of Direct Source-Drain Tunneling in MOSFETs / 3.4.1:
Future Trends in Post-6-nm MOSFETs / 3.4.2:
Conclusion / 3.5:
Quantum Effects in Silicon Nanodevices / Toshiro HiramotoChapter 4:
Quantum Effects in MOSFETs / 4.1:
Band Structures of Silicon / 4.2.1:
Surface Quantization / 4.2.2:
Carrier Confinement in Thin SOI MOS Structures / 4.2.3:
Mobility of Confined Carriers / 4.2.4:
Influences of Quantum Effects in MOSFETs / 4.3:
Threshold Voltage Increase in Bulk MOSFETs / 4.3.1:
Threshold Voltage Increase in FD-SOI MOSFETs / 4.3.2:
Mobility in Ultrathin FD-SOI MOSFETs / 4.3.3:
Quantum Effects in Ultranarrow Channel MOSFETs / 4.4:
Advantage of Quantum Effects in Ultranarrow Channel MOSFETs / 4.4.1:
Threshold Voltage Increase in n-Type Narrow Channel MOSFETs / 4.4.2:
Threshold Voltage Increase in n-Type and p-Type Narrow Channel MOSFETs / 4.4.3:
Threshold Voltage Adjustment Using Quantum Effects / 4.4.4:
Mobility Enhancement due to Quantum Effects / 4.4.5:
Ballistic Transport in Silicon Nanostructures / Hiroshi Mizuta ; Katsuhiko Nishiguchi ; Shunri Oda4.5:
Ballistic Transport in Quantum Point Contacts / 5.1:
Ballistic Transport in Ultra-Short Channel Vertical Silicon Transistors / 5.3:
Fabrication of Nanoscale Vertical FETs / 5.3.1:
Conductance Quantization in Nanoscale Vertical FETs / 5.3.2:
Characteristics under a Magnetic Field / 5.3.3:
Effects of Cross-Sectional Channel Geometries / 5.3.4:
Summary and Future Subjects / 5.4:
Resonant Tunneling in Si Nanodevices / Michiharu Tabe ; Hiroya Ikeda ; Yasuhiko IshikawaChapter 6:
Outline of Resonant Tunneling / 6.1:
Early Work on Resonant Tunneling / 6.1.1.1:
Resonant Tunneling in Si-Based Materials - Si/SiGe and Si/SiO[subscript 2] / 6.1.1.2:
Quantum Confinement Effect in a Thin Si Layer / 6.1.2:
Double-Barrier Structures of SiO[subscript 2]/Si/SiO[subscript 2] Formed by Anisotropic Etching / 6.1.3:
Resonant Tunneling in SiO[subscript 2]/Si/SiO[subscript 2] / 6.2:
Fabrication of an RTD / 6.2.1:
Resonant Tunneling in the Low Voltage Region / 6.2.2:
Hot-Electron Storage in the High-Voltage Region / 6.2.3:
Switching of Tunnel-Modes: Comparison with a Single Barrier / 6.2.4:
Zero-Dimensional Resonant Tunneling / 6.3:
Coexistence of Coulomb Blockade and Resonant Tunneling / 6.3.1:
Fabrication of a SiO[subscript 2]/Si-Dots/SiO[subscript 2] Structure / 6.3.2:
I-V Characteristics of an SiO[subscript 2]/Si-Dots/SiO[subscript 2] Tunnel Diode / 6.3.3:
Acknowledgment
Silicon Single-Electron Transistor and Memory / L. Jay GuoChapter 7:
Quantum Dot Transistor / 7.1:
Theoretical Background / 7.2:
Energy of the Quantum Dot System / 7.2.1:
Conductance Oscillation and Potential Fluctuation / 7.2.2:
Transport under Finite Temperature and Finite Bias / 7.2.3:
Device Structure and Fabrication / 7.3:
Experimental Results and Analysis / 7.4:
Single-Electron Quantum-Dot Transistor / 7.4.1:
Single-Hole Quantum-Dot Transistor / 7.4.2:
Transport Characteristics under Finite Bias / 7.4.3:
Transport Through Excited States / 7.4.4:
Artificial Atom / 7.5:
Single Charge Trapping / 7.6:
Introduction to Memory Devices / 7.7:
Floating Gate Scheme / 7.8:
Single-Electron MOS memory (SEMM) / 7.9:
Structure of SEMM / 7.9.1:
Fabrication Procedure / 7.9.2:
Experimental Observations / 7.9.3:
Analysis / 7.9.4:
Effects of Trap States / 7.9.5:
Effect of Thicker Tunnel Oxide / 7.10:
Discussion / 7.11:
Silicon Memories Using Quantum and Single-Electron Effects / Sandip TiwariChapter 8:
Single-Electron Effect / 8.1:
Single-Electron Transistors and Their Memories / 8.3:
Memories by Scaling Floating Gates of Flash Structures / 8.3.2:
Modeling of Transport: Tunneling / 8.4:
Tunneling in Oxide / 8.4.1:
Quantum Kinetic Equation / 8.4.2:
Carrier Statistics and Charge Fluctuations / 8.4.3:
Experimental Behavior of Memories / 8.5:
Percolation Effects / 8.5.1:
Limitations in Use of Field Effect / 8.5.2:
Confinement and Random Effects in Semiconductors / 8.5.3:
Variances due to Dimensions / 8.5.4:
Limits due to Tunneling / 8.5.5:
Tunneling in Silicon / 8.5.5.1:
Can We Avoid Use of Collective Phenomena? / 8.6:
SESO Memory Devices / Kazuo Yano8.7:
How Nanotechnologies Solve Real Problems / 9.1:
New Direction of Electronics / 9.1.2:
Conventional Memory Technologies / 9.2:
Classification of Conventional Memories / 9.2.1:
Origin of DRAM Power Consumption / 9.2.2:
Bandgap Enlargement in Nanosilicon / 9.3:
SESO Transistor / 9.4:
History: Single-Electron Devices to SESO / 9.4.1:
Fabricated SESO Transistor / 9.4.2:
SESO Memory / 9.5:
Memory-Technology Comparison / 9.6:
SESO as On-Chip RAM Component / 9.7:
Conclusions / 9.8:
Few Electron Devices and Memory Circuits / Kazuo Nakazato ; Haroon AhmedChapter 10:
Current Semiconductor Memories / 10.1:
Limitations of the DRAM / 10.2.1:
DRAM Gain Cell / 10.2.2:
A New DRAM Gain Cell - The PLEDM / 10.3:
PLEDTR / 10.3.1:
PLEDM Cell / 10.3.2:
Single-Electron Memory / 10.4:
Single-Electron Devices / 10.4.1:
Operation Principle of Single-Electron Memory / 10.4.2:
Local Stability / 10.4.2.1:
Global Stability / 10.4.2.2:
Experimental Single-Electron Memory / 10.4.3:
First Experimental Single-Electron Memory / 10.4.3.1:
Silicon Single-Electron Memory / 10.4.3.2:
Single-Electron Memory Array / 10.4.4:
Single-Electron Logic Devices / Yasuo Takahashi ; Yukinori Ono ; Akira Fujiwara ; Hiroshi Inokawa10.5:
Single-Electron Transistor (SET) / 11.1:
Fabrication of Si SETs / 11.3:
Logic Circuit Applications of SETs / 11.4:
Fundamentals of SET Logic / 11.4.1:
Merged SET and MOSFET Logic / 11.4.2:
CMOS-Type Logic Circuit / 11.4.3:
Pass-Transistor Logic / 11.4.4:
Multigate SET / 11.4.5:
Multiple-Valued Operation / 11.4.6:
Index / 11.5:
Physics of Silicon Nanodevices / David K. Ferry ; Richard Akis ; Matthew J. Gilbert ; Stephen M. RameyChapter 1:
Introduction / 1.1:
Small MOSFETs / 1.2:
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