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1.

図書
図書
1. Parallel architectures and compilation techniques
[conference organizers] Lubomir Bic ... [et al.]
出版情報: New York : ACM, [1995?]  xii, 314 p. ; 28 cm
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2.

図書
図書
2. Proceedings, 1997 International Conference on Parallel Architectures and Compilation Techniques, San Francisco, Calfornia, November 10-14, 1997
sponsors IFIP WG 10.3, IEEE Computer Society, ACM SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1997  ix, 319 p. ; 28 cm
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3.

図書
図書
3. Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques (PACT '96), October 20-23, 1996, Boston, Massachusetts (IEEE order plan ; microfiche)
sponsored by The IEEE Computer Society Technical Committee on Computer Architecture, IFIP WG 10.3 (Concurrent Systems), Association for Computing Machinery SIGARCH
出版情報: Los Alamitos, Calif. : IEEE Computer Society Press, c1996  xiv, 304 p. ; 28 cm
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4.

図書
図書
4. PACT 2005 : 14th International Conference on Parallel Architectures and Compilation Techniques, 17-21 September 2005, St.Louis, Missouri
sponsored by IEEE Computer Society... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2005  xv, 361 p. ; 28 cm
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5.

図書
図書
5. Parallel architectures and compilation techniques : proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Canada, 24-26 August, 1994
edited by Michel Cosnard, Guang R. Gao, Gabriel M. Silberman
出版情報: Amsterdam : North-Holland, 1994  xii, 362 p. ; 23 cm
シリーズ名: IFIP transactions ; A . Computer science and technology ; 50
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6.

図書
図書
6. Proceedings, 12th International Conference on Parallel Architectures and Compilation Techniques, PACT2003, 27 September -- 1 October 2003, New Orleans, Louisiana
sponsored by ACM SIGARCH... [et al.] ; corporate sponsors, Hewlett Packard...[et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2003  xiii, 279 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chairs
Message from the PC Chairs
Organizing Committee
Program Committee
Steering Committee
Reviewers
Single-Chip Multiprocessors: The Rebirth of Parallel Processing / G. SohiKeynote 1：
Multithreading / Session 1：
Constraint Graph Analysis of Multithreaded Programs / H. Cain ; M. Lipasti ; R. Nair
The Impact of Resource Partitioning on SMT Processors / S. Raasch ; S. Reinhardt
Initial Observations of a Simultaneous Multithreading Pentium 4 Processor / N. Tuck ; D. Tullsen
Instruction-Level Parallelism / Session 2：
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture / D.-Y. Chen ; L. Liu ; C. Fu ; S. Yang ; C. Wu ; R. Ju
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency / A. Aggarwal ; M. Franklin
Y-Branches: When You Come to a Fork in the Road, Take It / N. Wang ; M. Fertig ; S. Patel
Cache Optimizations / Session 3：
Optimizing Program Locality through CMEs and GAs / X. Vera ; J. Abella ; A. Gonzalez ; J. Llosa
Miss Rate Prediction across All Program Inputs / Y. Zhong ; S. Dropsho ; C. Ding
Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures / H. Al-Sukhni ; I. Bratt ; D. Connors
Challenges and New Approaches to Program Analysis / M. LamKeynote 2：
Compiler Techniques and Domain-Specific Optimizations / Session 4：
Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems / B. Franke ; M. O'Boyle
Inter-Procedural Loop Fusion, Array Contraction and Rotation / J. Ng ; D. Kulkarni ; W. Li ; R. Cox ; S. Bobholz
Spill Code Minimization by Spill Code Motion / A. Koseki ; H. Komatsu ; T. Nakatani
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on General-Purpose CPU / M. Breternitz, Jr ; H. Hum ; S. Kumar
Logging, Tracing, Profiling / Session 5：
An Efficient Online Path Profiling Framework for Java Just-in-Time Compilers / T. Yasue ; T. Suganuma
Compressing Extended Program Traces Using Value Predictors / M. Burtscher ; M. Jeeradit
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation / M. Garzaran ; M. Prvulovic ; V. Vinals ; J. Llaberia ; L. Rauchwerger ; J. Torrellas
Multiprocessors / Session 6：
Reactive Multi-Word Synchronization for Multiprocessors / P. Ha ; P. Tsigas
Design Trade-offs in High-Throughput Coherence Controllers / A.-T. Nguyen
Memory Hierarchy Design for a Multiprocessor Look-up Engine / J.-L. Baer ; D. Low ; P. Crowley ; N. Sidhwaney
Biomedical Computing and Visualization / C. JohnsonKeynote 3：
Application Characterization / Session 7：
Characterizing and Predicting Program Behavior and Its Variability / E. Duesterwald ; C. Cascaval ; S. Dwarkadas
Redeeming IPC as a Performance Metric for Multithreaded Programs / K. Lepak
Picking Statistically Valid and Early Simulation Points / E. Perelman ; G. Hamerly ; B. Calder
Register Design Issues / Session 8：
Reducing Datapath Energy through the Isolation of Short-Lived Operands / D. Ponomarev ; G. Kucuk ; O. Ergin ; K. Ghose
Resolving Register Bank Conflicts for a Network Processor / X. Zhuang ; S. Pande
Author Index
Message from the General Chairs
Message from the PC Chairs
Organizing Committee
7.

図書
図書
7. Proceedings, 2002 International Conference on Parallel Architectures and Compilatin Techniques, PACT2002, 22-25 September 2002, Charlottesville, Virginia, USA (: pbk)
sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xviii, 305 p. ; 28 cm
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目次情報: 続きを見る
Message from the General Chairs
Message from the Program Chairs
Organizing Committee
Steering Committee
Program Committee
Reviewers
Keynote Address
Parallelism in Mainstream Enterprise Platforms of the Future / D. Bhandarkar
Data Parallelism and Threading / Session 1：
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications / D. Chavarria-Miranda ; J. Mellor-Crummey
Increasing and Detecting Memory Address Congruence / S. Larsen ; E. Witchel ; S. Amarasinghe
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance / G. K. Dorai ; D. Yeung
Compiler Support for Architecture / Session 2：
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures / J. Shin ; J. Chame ; M. W. Hall
Effective Compilation Support for Variable Instruction Set Architecture / J. Liu ; T. Kong ; F. Chow
A Framework for Parallelizing Load/Stores on Embedded Processors / X. Zhuang ; S. Pande ; J. S. Greenland Jr.
Program Characterization / Session 3：
Workload Design: Selecting Representative Program-Input Pairs / L. Eeckhout ; H. Vandierendonck ; K. De Bosschere
Dataflow Frequency Analysis Based on Whole Program Paths / B. Scholz ; E. Mehofer
Quantifying Instruction Criticality / E. S. Tune ; D. M. Tullsen ; B. Calder
The Role of Computational Science in Energy Efficiency and Renewable Energy / S. Hammond
Power / Session 4：
Application Transformations for Energy and Performance-Aware Device Management / T. Heath ; E. Pinheiro ; J. Hom ; U. Kremer ; R. Bianchini
Leakage Energy Management in Cache Hierarchies / L. Li ; I. Kadayif ; Y-F. Tsai ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin ; A. Sivasubramaniam
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power / S. Dropsho ; A. Buyuktosunoglu ; R. Balasubramonian ; D. H. Albonesi ; S. Dwarkadas ; G. Semeraro ; G. Magklis ; M. L. Scott
Prediction / Session 5：
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors / M. E. Acacio ; J. Gonzalez ; J. M. Garcia ; J. Duato
Predicting Conditional Branches with Fusion-Based Hybrid Predictors / G. H. Loh ; D. S. Henry
Memory Performance / Session 6：
Speculative Sequential Consistency with Little Custom Storage / C. Gniady ; B. Falsafi
Cost-Effective Compiler Directed Memory Prefetching and Bypassing / D. Ortega ; E. Ayguade ; J.-L. Baer ; M. Valero
Using the Compiler to Improve Cache Replacement Decisions / Z. Wang ; K. S. McKinley ; A. L. Rosenberg ; C. C. Weems
Memory Aliasing / Session 7：
Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines / B. Goldberg ; E. Crutcher ; C. Huneycutt ; K. Palem
Speculative Alias Analysis for Executable Code / M. Fernandez ; R. Espasa
Cost Effective Memory Dependence Prediction Using Speculation Levels and Color Sets / S. Onder
The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources / R. Wolski
Java and IA-64 / Session 8：
Just-in-Time Java Compilation for the Itanium Processor / T. Shpeisman ; G.-Y. Lueh ; A.-R. Adl-Tabatabai
Eliminating Exception Constraints of Java Programs for IA-64 / K. Ishizaki ; T. Inagaki ; H. Komatsu ; T. Nakatani
Clustered Microarchitectures / Session 9：
Optimizing Loop Performance for Clustered VLIW Architectures / Y. Qian ; S. Carr ; P. Sweany
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning / A. Aleta ; J. M. Codina ; J. Sanchez ; A. Gonzalez ; D. Kaeli
Efficient Interconnects for Clustered Microarchitectures / J.-M. Parcerisa ; J. Sahuquillo
Sigarch Conference Guidelines
Author Index
Message from the General Chairs
Message from the Program Chairs
Organizing Committee
8.

図書
図書
8. Proceedings, 2000 International Conference on Parallel Architectures and Compilation Techniques, October 15-19, 2000, Philadelphia, Pennsylvania (: pbk)
sponsored by IEEE Technical Committee on Computer Architecture, IEEE Technical Committee on Parallel Processing ; in cooperation with ACM SIGARCH, IBM, Intel, SGI
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2000  xi, 309 p. ; 28 cm
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目次情報: 続きを見る
Introduction
Organizing Committee
Program Committee
Reviewers
Keynote
"New Challenges in Microarchitecture and Compiler Design" / Fred Pollack
Register Allocation and Analysis
Register Queues: A New Hardware/Software Approach To Efficient Software Pipelining / M. Smelyanskiy ; G. Tyson ; E. Davidson
Global Register Partitioning / J. Hiser ; S. Carr ; P. Sweany
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization / T. Way ; B. Breech ; L. Pollock
Architectural Design
aSOC: A Scalable, Single-Chip Communications Architecture / J. Liang ; S. Swaminathan ; R. Tessier
Address Partitioning in DSM Clusters with Parallel Coherence Controllers / I. Pragaspathy ; B. Falsafi
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications / B. Childers ; J. Davidson
Optimizations and Opportunities
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization / K. Hazelwood ; T. Conte
Exploring the Limits of Sub-Word Level Parallelism / K. Scott
The Dynamic Trace Memoization Reuse Technique / A. da Costa ; F. Franca ; E. Filho
Exploring Sub-Block Value Reuse for Superscalar Processors / J. Huang ; D. Lilja
"Dynamic Optimization: An Online Opportunity" / Michael Smith
High Performance Memory Techniques
Hiding Relaxed Memory Consistency with Compilers / J. Lee ; D. Padua
Neighborhood Prefetching on Multiprocessors Using Instruction History / D. Koppelman
Characterization of Silent Stores / G. Bell ; K. Lepak ; M. Lipasti
Speculation and Prediction
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors / S-J. Lee ; P-C. Yew
A Unified Compiler Framework for Control and Data Speculation / R. Ju ; K. Nomura ; U. Mahadevan ; L-C. Wu
Applying Data Speculation in Modulo Scheduled Loops / R. Hank
Branch Prediction
Branch Prediction in Multi-Threaded Processors / J. Gummaraju ; M. Franklin
The Effect of Code Reordering on Branch Prediction / A. Ramirez ; J. Larriba-Pey ; M. Valero
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions / K. Skadron ; M. Martonosi ; D. Clark
Dynamic Branch Prediction for a VLIW Processor / J. Hoogerbrugge
"Blue Gene" / Monty Denneau
Parallel Computation
Fine Grained Multithreading with Process Calculi / L. Lopes ; F. Silva ; V. Vasconcelos
Data Relation Vectors: A New Abstraction for Data Optimizations / M. Kandemir ; J. Ramanujam
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation / T. Kisuki ; P. Knijnenburg ; M. O'Boyle
Applications
Faster FFTs via Architecture-Cognizance / K. Gatlin ; L. Carter
Hybrid Parallel Circuit Simulation Approaches / E. Naroska ; R-J. Shang ; F. Lai ; U. Schwiegelshohn
Multithreaded Programming of PC Clusters / M. Schulz
Instruction Scheduling
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors / H. Wu ; J. Jaffar ; R. Yap
Instruction Scheduling for Clustered VLIW DSPs / R. Leupers
Efficient Backtracking Instruction Schedulers / S. Abraham ; W. Meleis ; I. Baev
Author Index
Introduction
Organizing Committee
Program Committee
9.

図書
図書
9. Proceedings, 2001 International Conference on Parallel Architectures and Compilatin Techniques, 8-12 September 2001, Barcelona, Catalunya, Spain (: pbk)
Sponsored by IEEE Computer Society Technical Committee on Computer Architecture, IEEE Computer Society Technical Commitee on Parallel Processing, ACM SIGARCH, IFIP Working Group 10.3 ; with the support of Technical University of Catalunya (UPC) ... [et al.]
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  x, 305 p. ; 28 cm
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目次情報: 続きを見る
General Chair's Message
Conference Organizers
Program Committee
Keynote Address / Randall D. Isaac
Simulation and Modeling / Session 1：
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications / T. Sherwood ; E. Perelman ; B. Calder
Modeling Superscalar Processors via Statistical Simulation / S. Nussbaum ; J. Smith
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces / L. Eeckhout ; K. De Bosschere
Efficient Caches / Session 2：
Filtering Techniques to Improve Trace-Cache Efficiency / R. Rosner ; A. Mendelson ; R. Ronen
Reactive-Associative Caches / B. Batson ; T. Vijaykumar
Adaptive Mode Control: A Static-Power-Efficient Cache Design / H. Zhou ; M. Toburen ; E. Rotenberg ; T. Conte
Specialized Instruction Sets / Session 3：
Implementation and Evaluation of the Complex Streamed Instruction Set / B. Juurlink ; D. Tcheressiz ; S. Vassiliadis ; H. Wijshoff
On the Efficiency of Reductions in [mu]-SIMD Media Extensions / J. Corbal ; R. Espasa ; M. Valero
Prediction and Recovery / Justin RattnerSession 4：
Boolean Formula-Based Branch Prediction for Future Technologies / D. Jimenez ; H. Hanson ; C. Lin
Using Dataflow Based Context for Accurate Value Prediction / R. Thomas ; M. Franklin
Recovery Mechanism for Latency Misprediction / E. Morancho ; J. Maria Llaberia ; A. Olive
Memory Optimization / Session 5：
A Cost Framework for Evaluating Integrated Restructuring Optimizations / B. Chandramouli ; J. Carter ; W. Hsieh ; S. McKee
Compiling for the Impulse Memory Controller / X. Huang ; Z. Wang ; K. McKinley
On the Stability of Temporal Data Reference Profiles / T. Chilimbi
Program Optimization / Session 6：
Code Reordering and Speculation Support for Dynamic Optimization Systems / E. Nystrom ; R. Barnes ; M. Merten ; W-M. Hwu
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors / J. Codina ; J. Sanchez ; A. Gonzalez
Cache-Friendly Implementations of Transitive Closure / M. Penner ; V. Prasanna
Technology Implications / Session 7：
Exploring the Design Space of Future CMPs / J. Huh ; D. Burger ; S. Keckler
Area and System Clock Effects on SMT/CMP Processors / J. Burns ; J-L. Gaudiot
Parallel Machines / Joel EmerSession 8：
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms / F. Warg ; P. Stenstrom
Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications / R. Ferreira ; G. Agrawal ; J. Saltz
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors / M. Garzaran ; M. Prvulovic ; Y. Zhang ; A. Jula ; H. Yu ; L. Rauchwerger ; J. Torrellas
Data Prefetching / Session 9：
Optimizing Software Data Prefetches with Rotating Registers / G. Doshi ; R. Krishnaiyer ; K. Muthukumar
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes / N. Kohout ; S. Choi ; D. Kim ; D. Yeung
Data Flow Analysis for Software Prefetching Linked Data Structures in Java / B. Cahoon
Comparing and Combining Read Miss Clustering and Software Prefetching / V. Pai ; S. Adve
Author Index
General Chair's Message
Conference Organizers
Program Committee
10.

図書
図書
10. Proceedings, 1999 International Conference on Parallel Architectures and Compilation Techniques, October 12-16, 1999, New port Beach, California
sponsored by IFIP and IEEE Computer Society
出版情報: Los Alamitos, Calif. : IEEE Computer society, c1999  xv, 321 p. ; 28 cm
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目次情報: 続きを見る
Message from the Chairs
Organizing Committee
Program Committee
Reviewers
Microarchitecture / Session 1：
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors / P. Michaud ; A. Seznec ; S. Jourdan
MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors / H. Oehring ; U. Sigmund ; T. Ungerer
A Fully Asynchronous Superscalar Architecture / D. Arvind ; R. Mullins
Multithreading / Session 2：
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors / V. Krishnan ; J. Torellas
A Multithreaded Java Microcontroller for Thread-Oriented Real-Time Event Handling / U. Brinkschulte ; C. Krakowski ; J. Kreuzinger
On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm / L. Codrescu ; D. Wills
Prediction Mechanisms / Session 3：
Branch Prediction Using Selective Branch Inversion / S. Manne ; A. Klauser ; D. Grunwald
Control-Flow Speculation through Value Prediction for Superscalar Processors / J. Gonzalez ; A. Gonzalez
Exploring Last n Value Prediction / M. Burtscher ; B. Zorn
Compilation Techniques / Session 4：
Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors / M. Valluri ; R. govindarajan
Containers on the Parallelization of General-Purpose Java Programs / P. Wu ; D. Padua
The Modulo Interval: A Simple and Practical Representation for Program Analysis / T. Nakanishi ; K. Joe ; C. Polychronopoulos ; A. Fukuda
Performance Characterization / Session 5：
Memory System Support for Image Processing / L. Zhang ; B. Carter ; W. Hsieh ; S. McKee
Performance Characteristics of a Network of Commodity Multiprocessors for the NAS Benchmarks Using a Hybrid Memory Model / F. Capello ; O. Richard
Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures / D. Ortega ; I. Martel ; E. Ayguade ; M. Valero
Invited Talk
High-End Computing Technology: Where is it Heading? / Greg Astfalk ; Hewlett-Packard Company
Advanced Compilation / Session 6：
LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation / B-S. Yang ; S-M. Moon ; S. Park ; J. Lee ; S. Lee ; J. Park ; Y. Chung ; S. Kim ; K. Ebcioglu ; E. Altman
Automatic Parallelization of Recursive Procedures / M. Gupta ; S. Mukhopadhyay ; N. Sinha
On the Complexity of Loop Fusion / A. Darte
Micro-Clusters, Clusters and SMPs / Session 7：
A Cost-Effective Clustered Architecture / R. Canal ; J-M. Parcerisa
Optimizing Data Locality for SCI-Based PC-Clusters with the SMiLE Monitoring Approach / W. Karl ; M. Leberecht ; M. Schultz
Dynamic Linking on a Shared-Memory Multiprocessor / B. Alpern ; M. Charney ; J-D. Choi ; A. Cocchi ; D. Lieber
Reducing Cache Conflicts by Partitioning and Privatizing Shared Arrays / Z. Li
Applied Analytical Techniques / Session 8：
Localizing Non-Affine Array References / N. Mitchell ; L. Carter ; J. Ferrante
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors / M. Kandemir ; A. Choudhary ; J. Ramanujam ; P. Banerjee
Lower Bounding Techniques for the Multiprocessor Scheduling Problem with Communication Delay / S. Fujita ; T. Nakagawa
Automatic Analytical Modeling for the Estimation of Cache Misses / B. Fraguela ; R. Doallo ; E. Zapata
Linux Alighted: Down to Earth Clusters / Beau Vrolyk ; Silicon Graphics
Architecture-Driven Compilation / Session 9：
Cameron: High level Language Compilation for Reconfigurable Systems / J. Hammes ; B. Rinker ; W. Bohm ; W. Najjar ; B. Draper ; R. Beveridge
Predicated Static Single Assignment / B. Simon ; B. Calder
The Effect of Program Optimization on Trace Cache Efficiency / D. Howard ; M. Lipasti
Advanced Parallelization / Session 10：
Data Dependence Testing in Practice / K. Psarris ; K. Kyriakopoulos
On Index Set Splitting / M. Griebl ; P. Feautrier ; C. Lenguaer
Efficient Parallelization Using Combined Loop and Data Transformations / M. O'boyle ; P. Knijnenburg
Predication and Speculation / Session 11：
Caching and Predicting Branch Sequences for Improved Fetch Effectiveness / S. Onder ; J. Xu ; R. Gupta
In Search of Speculative Thread-Level Parallelism / J. Oplinger ; D. Heine ; M. Lam
Looking at History to Filter Allocations in Prediction Tables / E. Morancho ; J. Maria Llaberia ; A. Olive
Author Index
Message from the Chairs
Organizing Committee
Program Committee
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