close
1.

図書
図書
1. Design, test, integration, and packaging of MEMS/MOEMS 2001 : 25-27 April 2001, Cannes, France
Bernard Courtois ... [et al.] chairs/editors ; sponsored by CNRS-INPG-UJF (France) ... [et al.]
出版情報: Bellingham, Washington : SPIE, c2001  xvi, 558 p. ; 28 cm
シリーズ名: Proceedings / SPIE -- the International Society for Optical Engineering ; v. 4408
所蔵情報: loading…
2.

図書
図書
2. Design, test, and microfabrication of MEMS and MOEMS : 30 March-1 April 1999, Paris, France (pt. 1 ; pt. 2)
Bernard Courtois ... [et. al.], chairs/editors ; sponsored by SPIE--The International Society for Optical Engineering, CNRS-INPG-UJF (France)
出版情報: Bellingham, Wash., USA : SPIE, c1999  2 v. ; 28 cm
シリーズ名: Proceedings / SPIE -- the International Society for Optical Engineering ; v. 3680
所蔵情報: loading…
3.

図書
図書
3. Design, characterization, and packaging for MEMS and microelectronics : 27-29 October 1999, Royal Pines Resort, Queensland, Australia
Bernard Courtois, Serge Demidenko, chairs/editors ; sponsored by SPIE--the International Society for Optical Engineering, IREE Society (Australia), Queensland Government State Development (Australia)
出版情報: Bellingham, Wash. : SPIE, c1999  x, 512 p. ; 28 cm
シリーズ名: Proceedings / SPIE -- the International Society for Optical Engineering ; v. 3893
所蔵情報: loading…
4.

図書
図書
4. Design, modeling, and simulation in microelectronics : 28-30 November 2000, Singapore
Bernard Courtois, Serge N. Demidenko, L.Y. Lau, chairs/editors ; sponsored by Nanyang Technological University (Singapore) [and] SPIE--the International Society for Optical Engineering ; cooperating organizations, Institute of Physics (Singapore) ... [et al.]
出版情報: Bellingham, Wash. : SPIE, c2000  xix, 393 p. ; 28 cm
シリーズ名: Proceedings / SPIE -- the International Society for Optical Engineering ; v. 4228
所蔵情報: loading…
5.

図書
図書
5. Design, test, integration, and packaging of MEMS/MOEMS 2002 : 6-8 May, 2002, Cannes, France
Bernard Courtois ... [et al.] chairs/editors ; sponsored by CNRS-INPG-UJF (France) ... [et al.]
出版情報: Bellingham, Wash. : SPIE, c2002  xvii, 832 p. ; 28 cm
シリーズ名: Proceedings / SPIE -- the International Society for Optical Engineering ; v. 4755
所蔵情報: loading…
6.

図書
図書
6. Proceedings, 2001 IEEE International Workshop on Memory Technology, Design and Testing, August 6-7, 2001, San Jose, California, USA (: case)
editors, Yervant Zorian ... [et al.] ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2001  viii, 108 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Message from the Chairs
Conference Committee
TTTC Information
Plenary Session
Memory Design / Session 1：
A DRAM Compiler for Fully Optimized Memory Instances / G. Harling
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme / K. Kim ; K. Rho ; K. Lee
Design of an Embedded Fully-Depleted SOI SRAM / R. Sung ; J. Koob ; T. Brandon ; D. Elliott ; B. Cockburn
Memory BIST / Session 2：
A P1500 Compliant Programable BistShell for Embedded Memories / S. Koranne ; C. Wouters ; T. Waayers ; S. Kumar ; R. Beurze ; G. Visweswaran
BIST-Based Bitfail Mapping of an Embedded DRAM / B. Kessler ; J. Dreibelbis ; T. McMahon ; J. McCloy ; R. Kho
Tutorial on Soft Error in Memories / Session 3：
Special Session on Memory Yield and Manufacturability / Session 4：
Redundancy and Error Control / Session 5：
A Method to Caculate Redundancy Coverage for FLASH Memory / S. Matarrese ; L. Fasoli
An Error Control Code Scheme for Multilevel Flash Memories / S. Gregori ; O. Khouri ; R. Micheloni ; G. Torelli
An Approach for Evaluation of Redunancy Analysis Algorithms / S. Shoukourian ; V. Vardanian ; Y. Zorian
Fault Models and Multi-Port SRAM Testing / Session 6：
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests / Z. Al-Ars ; A. van de Goor
Realistic Fault Models and Test Procedures for Multi-Port SRAMs / S. Hamdioui ; D. Eastwick ; M. Rodgers
A Parallel Approach for Testing Multi-Port Static Random Access Memories / F. Karimi ; S. Irrinki ; T. Crosby ; F. Lombardi
Verification and Test / Session 7：
Equivalence Checking a 256MB SDRAM / S. Napper ; D. Yang
Testing Carry Logic Modules of SRAM-based FPGAs / X. Sun ; J. Xu ; P. Trouborst
Low Output Resistance Charge Pump for Flash Memory Programming / D. Soltesz
Author Index
Message from the Chairs
Conference Committee
TTTC Information
7.

図書
図書
7. Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing : (MTDT 2002) : 10-12 July, 2002, Isle of Bendor, France (: bookbroker)
editors, Bernard Courtois, Thomas Wik, Yervant Zorian ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society
出版情報: Los Alamitos, Calif. : IEEE Computer Society, c2002  xii, 182 p. ; 28 cm
所蔵情報: loading…
目次情報: 続きを見る
Message from the Chairs
Conference Committee
TTTC Information
Joint Session with The Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)
Plenary Session / Session A：
Keynote Address: Embedded Memory Test and Repair / A. Kablanian
Memory BIST Analysis and Application / Session B：
Defect-Oriented Analysis of Memory BIST Tests / A. Jee
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D. Appello ; A. Fudoli ; V. Tancorre ; F. Corno ; M. Rebaudengo ; M. Sonza Reorda
A Scan-Bist Environment for Testing Embedded Memories / F. Karimi ; F. Lombardi
Memory ECC and Soft Errors / Session C：
Soft Error Protection for Embedded Memories / M. Nicolaidis
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories / D. Rossi ; C. Metra ; B. Ricco
High Speed 15 ns 4 Mbits SRAM for Space Application / B. Coloma ; P. Delaunay ; O. Husson
High Reliability in Railway and Automotive Systems / Session D：
The YATE Fail-Safe Interface: The User's Point of View / D. Bied-Charreton ; D. Guillon ; B. Jacques
Fault Tolerant Insertion and Verification: A Case Study / A. Manzone ; D. De Costantini
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems / L. Schiano ; D. Marino
Embedded Memory Yield Enhancement / Session E：
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios / E. Rondey ; Y. Tellier ; S. Borri
A March-Based Fault Location Algorithm for Static Random Access Memories / V. A. Vardanian ; Y. Zorian
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories / R.-F. Huang ; J.-F. Li ; J.-C. Yeh ; C.-W. Wu
MTDT
Keynote Address: Challenges and Opportunities Created by the SoC Shockwave / M. Templeton
Embedded Memory Systems and Test Optimization / Session 1：
Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch / R. Gibbins ; R. D. Adams ; T. Eckenrode ; M. Ouellette ; Y. Wu
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process / T. Kaya ; I. Shirakawa ; R. Miyamoto ; T. Onoye
Adder Merged DRAM Architecture / M. Hashimoto
Memory Test Strategies / Session 2：
March SS: A Test for All Static Simple RAM Faults / S. Hamdioui ; A. J. van de Goor ; M. Rodgers
Random Testing of Multi-Port Static Random Access Memories / F. J. Meyer
Fault Modeling / Session 3：
A Fault Modeling Technique to Test Memory BIST Algorithms / R. Venkatesh ; S. Kumar ; J. Philip ; S. Shukla
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM / M. Redeker ; B. F. Cockburn ; D. G. Elliott ; Y. Xiang ; S. A. Ung
An Investigation into Crosstalk Noise in DRAM Structures
Embedded Memory Compiler Tutorial / Session 4：
Keynote Address: SoC's Trends and Challenges going to 0.10 [mu]m / P. Magarshack
EPROM/EEPROM Design / Session 5：
An Automated Design Methodology for EEPROM Cell (ADE) / J. M. Portal ; L. Forli ; H. Aziza ; D. Nee
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology / C. Dray ; P. Gendrier
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories / C. Papaix ; J. M. Daga
Process Technology and Reliability / Session 6：
Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) / T. Devoivre ; M. Lunenborg ; C. Julien ; J-P. Carrere ; P. Ferreira ; W. J. Toren ; A. VandeGoor ; P. Gayet ; T. Berger ; O. Hinsinger ; P. Vannier ; Y. Trouiller ; Y. Rody ; P-J. Goirand ; R. Palla ; I. Thomas ; F. Guyader ; D. Roy ; B. Borot ; N. Planes ; S. Naudet ; F. Pico ; D. Duca ; F. Lalanne ; D. Heslinga ; M. Haond
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI / M. R. Casu ; P. Flatresse
Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact / R. Laffont ; J. Razafindramora ; P. Canet ; R. Bouchakour ; J. M. Mirabel
Advanced Memory Technologies Panel / Session 7：
Panel on Advanced Embedded Memory Technologies
Author Index
Message from the Chairs
Conference Committee
TTTC Information
文献の複写および貸借の依頼を行う
 文献複写・貸借依頼