Preface |
Workshop Committees |
TTTC: Test Technology Technical Council |
Functional Test Generation / Session A: |
Deep Trans--A Model-Based Approach to Functional Verification of Address Translation Mechanisms / A Adir ; R. Emek ; Y. Katz ; A. Koyfman |
Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification / M. Bose ; M. Nodine ; W. Jurasz, Jr. ; V. Zavadsky ; A. Chodavadia ; L. Nunes |
Definition of a Systematic Method for the Generation of Software Test Programs Allowing the Functional Verification of System on Chip (SoC) / F. Hunsinger ; S. Francois ; A. Jerraya |
Special Session, Research at University of Texas and Texas A&M / Session B: |
Testing the Path Delay Faults of ISCAS85 Circuit c6288 / W. Qiu ; D. Walker |
Keynote Speech / M. Gandhi, Sr. |
Issues in Microprocessor Test and Verification / Session C: |
Comparison of Verification Methodologies for Datapath Testing / V. Iyer |
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits / J. Bhadra ; N. Krishnamurthy ; M. Abadir |
Utilizing Various ADL Facets for Instruction Level CPU Test / E. Safi ; Z. Karimi ; M. Abbaspour ; Z. Navabi |
Debug and Diagnosis / Session E: |
Automatic Detection of Logic Bugs in Hardware Designs / A. Klaiber ; S. Chau |
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs / Y.-S. Yang ; J. Liu ; P. Thadikaran ; A. Veneris |
Fault Diagnosis and Logic Debugging Using Boolean Satisfiability |
SAT and ATPG / Session F: |
Heuristic Backtracking Algorithms for SAT / A. Bhalla ; I. Lynce ; J. de Sousa ; J. Marques-Silva |
Tuning the VSIDS Decision Heuristic for Bounded Model Checking / O. Shacham ; E. Zarpas |
Embedded System Validation / Session G: |
A Methodology for Validation of Microprocessors Using Equivalence Checking / P. Mishra ; N. Dutt |
A SystemC-Based Framework for Properties Incompleteness Evaluation / A. Fin ; F. Fummi ; M. Poncino ; G. Pravadelli |
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification / M. Iyer |
Simulation Techniques / Session H: |
Systematic Abstractions of Microprocessor RTL Models to Enhance Simulation Efficiency / D. Bhaduri ; M. Chandra ; H. Patel ; S. Sharad ; S. Suhaib |
Case Study / Session I: |
Energy Awareness through Software Optimisation as a Performance Estimate Case Study of the MC68HC908GP32 Microcontroller / J. Oliver ; O. Mocanu ; C. Ferrer |
High-Level Verification / Session K: |
A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture / M. Heath ; I. Harris |
Author Index |
Preface |
Workshop Committees |
TTTC: Test Technology Technical Council |