| Introduction |
| Organizing Committee |
| Program Committee |
| Reviewers |
| Keynote |
| "New Challenges in Microarchitecture and Compiler Design" / Fred Pollack |
| Register Allocation and Analysis |
| Register Queues: A New Hardware/Software Approach To Efficient Software Pipelining / M. Smelyanskiy ; G. Tyson ; E. Davidson |
| Global Register Partitioning / J. Hiser ; S. Carr ; P. Sweany |
| Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization / T. Way ; B. Breech ; L. Pollock |
| Architectural Design |
| aSOC: A Scalable, Single-Chip Communications Architecture / J. Liang ; S. Swaminathan ; R. Tessier |
| Address Partitioning in DSM Clusters with Parallel Coherence Controllers / I. Pragaspathy ; B. Falsafi |
| Custom Wide Counterflow Pipelines for High-Performance Embedded Applications / B. Childers ; J. Davidson |
| Optimizations and Opportunities |
| A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization / K. Hazelwood ; T. Conte |
| Exploring the Limits of Sub-Word Level Parallelism / K. Scott |
| The Dynamic Trace Memoization Reuse Technique / A. da Costa ; F. Franca ; E. Filho |
| Exploring Sub-Block Value Reuse for Superscalar Processors / J. Huang ; D. Lilja |
| "Dynamic Optimization: An Online Opportunity" / Michael Smith |
| High Performance Memory Techniques |
| Hiding Relaxed Memory Consistency with Compilers / J. Lee ; D. Padua |
| Neighborhood Prefetching on Multiprocessors Using Instruction History / D. Koppelman |
| Characterization of Silent Stores / G. Bell ; K. Lepak ; M. Lipasti |
| Speculation and Prediction |
| On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors / S-J. Lee ; P-C. Yew |
| A Unified Compiler Framework for Control and Data Speculation / R. Ju ; K. Nomura ; U. Mahadevan ; L-C. Wu |
| Applying Data Speculation in Modulo Scheduled Loops / R. Hank |
| Branch Prediction |
| Branch Prediction in Multi-Threaded Processors / J. Gummaraju ; M. Franklin |
| The Effect of Code Reordering on Branch Prediction / A. Ramirez ; J. Larriba-Pey ; M. Valero |
| A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions / K. Skadron ; M. Martonosi ; D. Clark |
| Dynamic Branch Prediction for a VLIW Processor / J. Hoogerbrugge |
| "Blue Gene" / Monty Denneau |
| Parallel Computation |
| Fine Grained Multithreading with Process Calculi / L. Lopes ; F. Silva ; V. Vasconcelos |
| Data Relation Vectors: A New Abstraction for Data Optimizations / M. Kandemir ; J. Ramanujam |
| Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation / T. Kisuki ; P. Knijnenburg ; M. O'Boyle |
| Applications |
| Faster FFTs via Architecture-Cognizance / K. Gatlin ; L. Carter |
| Hybrid Parallel Circuit Simulation Approaches / E. Naroska ; R-J. Shang ; F. Lai ; U. Schwiegelshohn |
| Multithreaded Programming of PC Clusters / M. Schulz |
| Instruction Scheduling |
| A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors / H. Wu ; J. Jaffar ; R. Yap |
| Instruction Scheduling for Clustered VLIW DSPs / R. Leupers |
| Efficient Backtracking Instruction Schedulers / S. Abraham ; W. Meleis ; I. Baev |
| Author Index |
| Introduction |
| Organizing Committee |
| Program Committee |
| Reviewers |
| Keynote |
| "New Challenges in Microarchitecture and Compiler Design" / Fred Pollack |
