| Preface |
| Editorial Board |
| ATS 1992 |
| An Approach to Design-for-Testability for Memory Embedding Logic LSIs / K. Hatayama ; T. Hayashi ; M. Takakura ; T. Suzuki ; S. Michishita ; H. Satoh |
| Synthesis for Testability of PLA Based Finite State Machines / M. Avedillo ; J. Quintana ; J. Huertas |
| A Concurrent Fault Detection Method for Superscalar Processors / A. Pawlovsky ; M. Hanawa |
| A Method of Diagnosing Logical Faults in Combinational Circuits / K. Yamazaki ; T. Yamada |
| Reduction of Dynamic Memory Usage in Concurrent Fault Simulation for Synchronous Sequential Circuits / K. Kim ; K. Saluja |
| ATS 1993 |
| Test Set Partitioning and Dynamic Fault Dictionaries for Sequential Circuits / P. Ryan ; W. Fuchs |
| A Two-Phase Fault Simulation Scheme for Sequential Circuits / W. Wu ; C. Lee ; J. Chen |
| GID-Testable Two-Dimensional Sequential Arrays for Self-Testing / W. Huang ; F. Lombardi ; M. Lu |
| A Global BIST Methodology / T. Gheewala ; H. Sucar ; P. Varma |
| On Properties and Implementations of Inverting ALSC for Use in Built-in Self-Testing / K. Furuya ; P. Koh ; E. McCluskey |
| ATS 1994 |
| Efficient Test Sequence Generation for Localization of Multiple Faults in Communication Protocols / Y. Kakuda ; H. Yukitomo ; S. Kusumoto ; T. Kikuno |
| Design of Random Pattern Testable Floating Point Adders / J. Rajski ; J. Tyszer |
| Testability Considerations in Technology Mapping / I. Pomeranz ; S. Reddy |
| Analysis and Improvement of Testability Measure Approximation Algorithms / J. Bitner ; J. Jain ; J. Abraham ; D. Fussell |
| Efficiency Improvements for Multiple Fault Diagnosis of Combinational Circuits / N. Yanagida ; H. Takahashi ; Y. Takamatsu |
| Boolean Process--An Analytical Approach to Circuit Representation / Y. Min |
| ATS 1995 |
| Software Transformations for Sequential Test Generation / A. Balakrishnan ; S. Chakradhar |
| DC Control and Observation Structures for Analog Circuits / Y.-R. Shieh ; C.-W. Wu |
| Universal Test Complexity of Field-Programmable Gate Arrays / T. Inoue ; H. Fujiwara ; H. Michinishi ; T. Yokohira ; T. Okamoto |
| A Design-for-Test Technique for Multi-stage Analog Circuits / M. Renovell ; F. Azais ; Y. Bertrand |
| Fanout Fault Analysis for Digital Logic Circuits / W. Shen ; B. Chen |
| Theory and Applications of Cellular Automata for Synthesis of Easily Testable Combinational Logic / S. Nandi ; P. Chaudhuri |
| Low Power Design and Its Testability / H. Ueda ; K. Kinoshita |
| ATS 1996 |
| Redundancy Identification Using Transitive Closure / V. Agrawal ; M. Bushnell ; Q. Lin |
| A Consistent Scan Design System for Large-Scale ASICs / Y. Konno ; K. Nakamura ; T. Bitoh ; K. Saga ; S. Yano |
| Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults / K.-J. Lee ; J.-J. Tang ; T.-C. Huang ; C.-L. Tsai |
| Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique / Y. Higami ; S. Kajihara |
| An Efficient Compact Test Generator for I[subscript DDQ] Testing / H. Kondo ; K.-T. Cheng |
| ATS 1997 |
| FaultMaxx: A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits / N. Ben-Hamida ; K. Saab ; D. Marche ; B. Kaminska |
| On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs / S. Miyazaki |
| Testing for the Programming Circuit of LUT-Based FPGAs |
| Test Length for Random Testing of Sequential Machines Application to RAMs / R. David |
| A Genetic Algorithm for Computation of Initialization Sequences for Synchronous Sequential Circuits / F. Corno ; P. Prinetto ; M. Rebaudengo ; M. Reorda ; G. Squillero |
| On Chip Weighted Random Patterns / J. Savir |
| ATS 1998 |
| Vector Restoration Using Accelerated Validation and Refinement / S. Bommu ; K. Doreswamy |
| March LA: A Test for All Linked Memory Faults / A. van de Goor ; G. Gaydadjiev ; V. Yarmolik ; V. Mikitjuk |
| Test Cycle Count Reduction in a Parallel Scan BIST Environment / B. Ayari |
| BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level / C.-H. Chiang ; S. Gupta |
| False-Path Removal Using Delay Fault Simulation / M. Gharaybeh |
| A Ring Architecture Strategy for BIST Test Pattern Generation / C. Fagot ; O. Gascuel ; P. Girard ; C. Landrault |
| ATS 1999 |
| High Resolution CD-SEM System / Y. Ose ; M. Ezumi ; H. Todokoro |
| An Evaluation of Test Generation Algorithms for Combinational Circuits / S. Xu ; T. Frank |
| An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits / H.-C. Liang |
| Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption / L. Guiller ; S. Pravossoudovitch |
| New DFT Techniques of Non-scan Sequential Circuits with Complete Fault Efficiency / D. Das ; S. Ohtake |
| ATS 2000 |
| Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen ; M. Breuer |
| A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue ; E. Gizdarski |
| Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris ; J. Collins ; A. Orailoglu |
| A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen |
| Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang |
| ATS 2001 |
| Short Circuit Faults in State-of-the-Art ADCs--Are They Hard or Soft? / A. Lechner ; A. Richardson ; B. Hermes |
| EB-Testing-Pad Method and Its Evaluation by Actual Devices / N. Kuji ; T. Ishihara |
| Robust Self Concurrent Test of Linear Digital Systems / E. Simeu ; A. Abdelhay ; M. Naal |
| Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design / Y. Huang ; W.-T. Cheng ; C.-C. Tsai ; N. Mukherjee ; O. Samman ; Y. Zaidan |
| Design for Hierarchical Two-Pattern Testability of Data Paths / Md. Altaf-Ul-Amin |
| Author Index |
| Preface |
| Editorial Board |
| ATS 1992 |
| An Approach to Design-for-Testability for Memory Embedding Logic LSIs / K. Hatayama ; T. Hayashi ; M. Takakura ; T. Suzuki ; S. Michishita ; H. Satoh |
| Synthesis for Testability of PLA Based Finite State Machines / M. Avedillo ; J. Quintana ; J. Huertas |
| A Concurrent Fault Detection Method for Superscalar Processors / A. Pawlovsky ; M. Hanawa |
